/**************************************************************************
**                                                                        *
**  FILE            : regtc1782.sfr                                       *
**                                                                        *
**  DESCRIPTION     : Include file with memory mapped I/O definitions     *
**                    for the TC1782.                                     *
**                                                                        *
**  Copyright 2007 Altium BV                                               *
**                                                                        *
**************************************************************************/
#ifndef _REGTC1782_H
#define _REGTC1782_H

#define core_base 0xF7E1        /* the base address off the memory for the CSFR's */

/* Core SFRs */
/* the following core SFR's can only be accessed thru the MFCR and MTCR functions */

#define PCX		0xFE00  /* Previous Context Info Register */
#define PCXI    0xFE00  /* Previous Context Info Register */
#define PSW     0xFE04  /* Program Status Word */
#define PC      0xFE08  /* Program Counter */
#define SYSCON  0xFE14  /* System Configuration Control Register */
#define CPU_ID  0xFE18  /* CPU Identification Register */
#define BIV     0xFE20  /* Interrupt Vector Table */
#define BTV     0xFE24  /* Trap Vector Table Pointer. */
#define ISP     0xFE28  /* Interrupt Stack Pointer */
#define ICR     0xFE2C  /* Interrupt Unit Control Register */
#define FCX     0xFE38  /* Free CSA List Head Pointer */
#define LCX     0xFE3C  /* Free CSA List Limit Pointer */


/* Core Special Function Registers (CSFR) */
#define DPR0_0L	0xc000	/* Data Segment Protection Register Set 0, Range 0, Lower Boundary  */
#define DPR0_1L	0xc008	/* Data Segment Protection Register Set 0, Range 1, Lower Boundary  */
#define DPR0_2L	0xc010	/* Data Segment Protection Register Set 0, Range 2, Lower Boundary  */
#define DPR0_3L	0xc018	/* Data Segment Protection Register Set 0, Range 3, Lower Boundary  */
#define DPR1_0L	0xc400	/* Data Segment Protection Register Set 1, Range 0, Lower Boundary  */
#define DPR1_1L	0xc408	/* Data Segment Protection Register Set 1, Range 1, Lower Boundary  */
#define DPR1_2L	0xc410	/* Data Segment Protection Register Set 1, Range 2, Lower Boundary  */
#define DPR1_3L	0xc418	/* Data Segment Protection Register Set 1, Range 3, Lower Boundary  */
#define DPR0_0U	0xc004	/* Data Segment Protection Register Set 0, Range 0, Upper Boundary  */
#define DPR0_1U	0xc00c	/* Data Segment Protection Register Set 0, Range 1, Upper Boundary  */
#define DPR0_2U	0xc014	/* Data Segment Protection Register Set 0, Range 2, Upper Boundary  */
#define DPR0_3U	0xc01c	/* Data Segment Protection Register Set 0, Range 3, Upper Boundary  */
#define DPR1_0U	0xc404	/* Data Segment Protection Register Set 1, Range 0, Upper Boundary  */
#define DPR1_1U	0xc40c	/* Data Segment Protection Register Set 1, Range 1, Upper Boundary  */
#define DPR1_2U	0xc414	/* Data Segment Protection Register Set 1, Range 2, Upper Boundary  */
#define DPR1_3U	0xc41c	/* Data Segment Protection Register Set 1, Range 3, Upper Boundary  */
#define DPR2_0L	0xc800	/* Data Segment Protection Register Set 2, Range 0, Lower Boundary  */
#define DPR2_1L	0xc808	/* Data Segment Protection Register Set 2, Range 1, Lower Boundary  */
#define DPR2_2L	0xc810	/* Data Segment Protection Register Set 2, Range 2, Lower Boundary  */
#define DPR2_3L	0xc818	/* Data Segment Protection Register Set 2, Range 3, Lower Boundary  */
#define DPR3_0L	0xcc00	/* Data Segment Protection Register Set 3, Range 0, Lower Boundary  */
#define DPR3_1L	0xcc08	/* Data Segment Protection Register Set 3, Range 1, Lower Boundary  */
#define DPR3_2L	0xcc10	/* Data Segment Protection Register Set 3, Range 2, Lower Boundary  */
#define DPR3_3L	0xcc18	/* Data Segment Protection Register Set 3, Range 3, Lower Boundary  */
#define DPR2_0U	0xc804	/* Data Segment Protection Register Set 2, Range 0, Upper Boundary  */
#define DPR2_1U	0xc80c	/* Data Segment Protection Register Set 2, Range 1, Upper Boundary  */
#define DPR2_2U	0xc814	/* Data Segment Protection Register Set 2, Range 2, Upper Boundary  */
#define DPR2_3U	0xc81c	/* Data Segment Protection Register Set 2, Range 3, Upper Boundary  */
#define DPR3_0U	0xcc04	/* Data Segment Protection Register Set 3, Range 0, Upper Boundary  */
#define DPR3_1U	0xcc0c	/* Data Segment Protection Register Set 3, Range 1, Upper Boundary  */
#define DPR3_2U	0xcc14	/* Data Segment Protection Register Set 3, Range 2, Upper Boundary  */
#define DPR3_3U	0xcc1c	/* Data Segment Protection Register Set 3, Range 3, Upper Boundary  */
#define CPR0_0L	0xd000	/* Code Segment Protection Register Set 0, Range 0, Lower Boundary  */
#define CPR0_1L	0xd008	/* Code Segment Protection Register Set 0, Range 1, Lower Boundary  */
#define CPR1_0L	0xd400	/* Code Segment Protection Register Set 1, Range 0, Lower Boundary  */
#define CPR1_1L	0xd408	/* Code Segment Protection Register Set 1, Range 1, Lower Boundary  */
#define CPR2_0L	0xd800	/* Code Segment Protection Register Set 2, Range 0, Lower Boundary  */
#define CPR2_1L	0xd808	/* Code Segment Protection Register Set 2, Range 1, Lower Boundary  */
#define CPR3_0L	0xdc00	/* Code Segment Protection Register Set 3, Range 0, Lower Boundary  */
#define CPR3_1L	0xdc08	/* Code Segment Protection Register Set 3, Range 1, Lower Boundary  */
#define CPR0_0U	0xd004	/* Code Segment Protection Register Set 0, Range 0, Upper Boundary  */
#define CPR0_1U	0xd00c	/* Code Segment Protection Register Set 0, Range 1, Upper Boundary  */
#define CPR1_0U	0xd404	/* Code Segment Protection Register Set 1, Range 0, Upper Boundary  */
#define CPR1_1U	0xd40c	/* Code Segment Protection Register Set 1, Range 1, Upper Boundary  */
#define CPR2_0U	0xd804	/* Code Segment Protection Register Set 2, Range 0, Upper Boundary  */
#define CPR2_1U	0xd80c	/* Code Segment Protection Register Set 2, Range 1, Upper Boundary  */
#define CPR3_0U	0xdc04	/* Code Segment Protection Register Set 3, Range 0, Upper Boundary  */
#define CPR3_1U	0xdc0c	/* Code Segment Protection Register Set 3, Range 1, Upper Boundary  */
#define DPM0	0xe000	/* Data Protection Mode Register Set 0  */
#define DPM1	0xe080	/* Data Protection Mode Register Set 1  */
#define DPM2	0xe100	/* Data Protection Mode Register Set 2  */
#define DPM3	0xe180	/* Data Protection Mode Register Set 3  */
#define CPM0	0xe200	/* Code Protection Mode Register Set 0  */
#define CPM1	0xe280	/* Code Protection Mode Register Set 1  */
#define CPM2	0xe300	/* Code Protection Mode Register Set 2  */
#define CPM3	0xe380	/* Code Protection Mode Register Set 3  */
#define DBGSR	0xfd00	/* Debug Status Register  */
#define EXEVT	0xfd08	/* External Event Register  */
#define CREVT	0xfd0c	/* External Event Register  */
#define SWEVT	0xfd10	/* External Event Register  */
#define TR0EVT	0xfd20	/* Trigger Event 0 Register  */
#define TR1EVT	0xfd24	/* Trigger Event 1 Register  */
#define DMS	0xfd40	/* Debug Monitor Start Address Register  */
#define DCX	0xfd44	/* Debug Context Save Area Pointer Register  */
#define DBGTCR	0xfd48	/* Debug Trap Control Register  */
#define CCTRL	0xfc00	/* Counter Control Register  */
#define CCNT	0xfc04	/* CPU Clock Count Register  */
#define ICNT	0xfc08	/* Instruction Count Register  */
#define M1CNT	0xfc0c	/* Multi-Count Register 1  */
#define M2CNT	0xfc10	/* Multi-Count Register 2  */
#define M3CNT	0xfc14	/* Multi-Count Register 3  */
#define MMU_CON	0x8000	/* MMU Control Register  */
#define MIECON	0x9044	/* Memory Integrity Error Control Register  */
#define CCPIER	0x9218	/* Count of Corrected Program Integrity Errors Register  */
#define CCDIER	0x9028	/* Count of Corrected Data Integrity Errors Register  */
#define PIETR	0x9214	/* Program Integrity Error Trap Register  */
#define PIEAR	0x9210	/* Program Integrity Error Address Register  */
#define DIETR	0x9024	/* Data Integrity Error Trap Register  */
#define DIEAR	0x9020	/* Data Integrity Error Address Register  */
#define SMACON	0x900c	/* SIST Mode Access Control Register  */
#define BMACON	0x9004	/* BIST Mode Access Control Register  */
#define FPU_TRAP_CON	0xa000	/* Trap Control Register  */
#define FPU_TRAP_PC	0xa004	/* Trapping Instruction Program Counter Register  */
#define FPU_TRAP_OPC	0xa008	/* Trapping Instruction Opcode Register  */
#define FPU_TRAP_SRC1	0xa010	/* Trapping Instruction Operand Register  */
#define FPU_TRAP_SRC2	0xa014	/* Trapping Instruction Operand Register  */
#define FPU_TRAP_SRC3	0xa018	/* Trapping Instruction Operand Register  */
#define FPU_ID	0xa020	/* Trapping Identification Register  */
#define COMPAT	0x9400	/* Compatibility Control Register  */

/* CPU */
typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 MOD_REV        : 8;
		/* const */ unsigned __sfrbit32 MOD_32B        : 8;
		/* const */ unsigned __sfrbit32 MOD            : 16;
	} B;
	int I;
	unsigned int U;

} CPS_ID_type;
#define CPS_ID	(*(CPS_ID_type*) 0xf7e0ff08u)	/* CPS Module Identification Register  */
#define DMI_ID	(*(CPS_ID_type*) 0xf87ffc08u)	/* DMI Identification Register  */
#define PMI_ID	(*(CPS_ID_type*) 0xf87ffd08u)	/* PMI Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 SRPN           : 8;
		unsigned __sfrbit32                : 2;
		unsigned __sfrbit32 TOS            : 1;
		unsigned __sfrbit32                : 1;
		unsigned __sfrbit32 SRE            : 1;
		/* const */ unsigned __sfrbit32 SRR            : 1;
		unsigned __sfrbit32 CLRR           : 1;
		unsigned __sfrbit32 SETR           : 1;
		unsigned __sfrbit32                : 16;
	} B;
	int I;
	unsigned int U;

} CPU_SBSRC_type;
#define CPU_SBSRC	(*(CPU_SBSRC_type*) 0xf7e0ffbcu)	/* CPU Software Breakpoint Service Request Control Register  */
#define CPU_SRC0	(*(CPU_SBSRC_type*) 0xf7e0fffcu)	/* CPU Service Request Control Register 0  */
#define CPU_SRC1	(*(CPU_SBSRC_type*) 0xf7e0fff8u)	/* CPU Service Request Control Register 1  */
#define CPU_SRC2	(*(CPU_SBSRC_type*) 0xf7e0fff4u)	/* CPU Service Request Control Register 2  */
#define CPU_SRC3	(*(CPU_SBSRC_type*) 0xf7e0fff0u)	/* CPU Service Request Control Register 3  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 SREATF         : 1;
		/* const */ unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 SBEATF         : 1;
		/* const */ unsigned __sfrbit32                : 3;
		/* const */ unsigned __sfrbit32 CRSEATF        : 1;
		/* const */ unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 CWSEATF        : 1;
		/* const */ unsigned __sfrbit32 CFEATF         : 1;
		/* const */ unsigned __sfrbit32 CMEATF         : 1;
		/* const */ unsigned __sfrbit32                : 3;
		/* const */ unsigned __sfrbit32 SMEATF         : 1;
		/* const */ unsigned __sfrbit32                : 16;
	} B;
	int I;
	unsigned int U;

} DMI_ATR_type;
#define DMI_ATR	(*(DMI_ATR_type*) 0xf87ffc20u)	/* DMI Asynchronous Trap Flag Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 DC_SZ_AV       : 4;
		/* const */ unsigned __sfrbit32 DMEM_SZ_AV     : 12;
		unsigned __sfrbit32 DC_SZ_CFG      : 4;
		unsigned __sfrbit32 DMEM_SZ_CFG    : 12;
	} B;
	int I;
	unsigned int U;

} DMI_CON_type;
#define DMI_CON	(*(DMI_CON_type*) 0xf87ffc10u)	/* DMI Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 LRESTF         : 1;
		/* const */ unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 LBESTF         : 1;
		/* const */ unsigned __sfrbit32                : 3;
		/* const */ unsigned __sfrbit32 CRLESTF        : 1;
		/* const */ unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 CWLESTF        : 1;
		/* const */ unsigned __sfrbit32                : 5;
		/* const */ unsigned __sfrbit32 LMESTF         : 1;
		/* const */ unsigned __sfrbit32                : 17;
	} B;
	int I;
	unsigned int U;

} DMI_STR_type;
#define DMI_STR	(*(DMI_STR_type*) 0xf87ffc18u)	/* DMI Synchronous Trap Flag Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32                : 1;
		unsigned __sfrbit32 PCBYP          : 1;
		unsigned __sfrbit32                : 30;
	} B;
	int I;
	unsigned int U;

} PMI_CON0_type;
#define PMI_CON0	(*(PMI_CON0_type*) 0xf87ffd10u)	/* PMI Control Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 PCINV          : 1;
		unsigned __sfrbit32 PBINV          : 1;
		unsigned __sfrbit32                : 30;
	} B;
	int I;
	unsigned int U;

} PMI_CON1_type;
#define PMI_CON1	(*(PMI_CON1_type*) 0xf87ffd14u)	/* PMI Control Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 PC_SZ_AV       : 4;
		/* const */ unsigned __sfrbit32 PMEM_SZ_AV     : 12;
		unsigned __sfrbit32 PC_SZ_CFG      : 4;
		unsigned __sfrbit32 PMEM_SZ_CFG    : 12;
	} B;
	int I;
	unsigned int U;

} PMI_CON2_type;
#define PMI_CON2	(*(PMI_CON2_type*) 0xf87ffd18u)	/* PMI Control Register 2  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 FRESTF         : 1;
		/* const */ unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 FBESTF         : 1;
		/* const */ unsigned __sfrbit32                : 9;
		/* const */ unsigned __sfrbit32 FPESTF         : 1;
		/* const */ unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 FMESTF         : 1;
		/* const */ unsigned __sfrbit32                : 17;
	} B;
	int I;
	unsigned int U;

} PMI_STR_type;
#define PMI_STR	(*(PMI_STR_type*) 0xf87ffd20u)	/* PMI Synchronous Trap Register  */


/* SCU */
typedef volatile union
{
	struct
	{ 
		unsigned int STMDIS         : 1;
		unsigned int                : 31;
	} B;
	int I;
	unsigned int U;

} SCU_ARSTDIS_type;
#define SCU_ARSTDIS	(*(SCU_ARSTDIS_type*) 0xf000055cu)	/* Application Reset Disable Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int FPIDIV         : 4;
		unsigned int                : 4;
		unsigned int LMBDIV         : 4;
		unsigned int                : 19;
		/* const */ unsigned int LCK            : 1;
	} B;
	int I;
	unsigned int U;

} SCU_CCUCON0_type;
#define SCU_CCUCON0	(*(SCU_CCUCON0_type*) 0xf0000530u)	/* CCU Clock Control Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int MCDSDIV        : 4;
		unsigned int                : 4;
		/* const */ unsigned int REFCLKDIV      : 4;
		unsigned int                : 19;
		/* const */ unsigned int LCK            : 1;
	} B;
	int I;
	unsigned int U;

} SCU_CCUCON1_type;
#define SCU_CCUCON1	(*(SCU_CCUCON1_type*) 0xf0000534u)	/* CCU Clock Control Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int CHREV          : 8;
		unsigned int CHID           : 8;
		/* const */ unsigned int EEA            : 1;
		unsigned int                : 15;
	} B;
	int I;
	unsigned int U;

} SCU_CHIPID_type;
#define SCU_CHIPID	(*(SCU_CHIPID_type*) 0xf0000640u)	/* Chip Identification Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RESULT         : 10;
		/* const */ unsigned int                : 4;
		/* const */ unsigned int RDY            : 1;
		/* const */ unsigned int BUSY           : 1;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SCU_DTSSTAT_type;
#define SCU_DTSSTAT	(*(SCU_DTSSTAT_type*) 0xf00005e0u)	/* Die Temperature Sensor Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int EXIS0          : 2;
		unsigned int                : 2;
		unsigned int FEN0           : 1;
		unsigned int REN0           : 1;
		unsigned int LDEN0          : 1;
		unsigned int EIEN0          : 1;
		unsigned int INP0           : 3;
		unsigned int                : 5;
		unsigned int EXIS1          : 2;
		unsigned int                : 2;
		unsigned int FEN1           : 1;
		unsigned int REN1           : 1;
		unsigned int LDEN1          : 1;
		unsigned int EIEN1          : 1;
		unsigned int INP1           : 3;
		unsigned int                : 1;
	} B;
	int I;
	unsigned int U;

} SCU_EICR0_type;
#define SCU_EICR0	(*(SCU_EICR0_type*) 0xf0000580u)	/* External Input Channel Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int EXIS2          : 2;
		unsigned int                : 2;
		unsigned int FEN2           : 1;
		unsigned int REN2           : 1;
		unsigned int LDEN2          : 1;
		unsigned int EIEN2          : 1;
		unsigned int INP2           : 3;
		unsigned int                : 5;
		unsigned int EXIS3          : 2;
		unsigned int                : 2;
		unsigned int FEN3           : 1;
		unsigned int REN3           : 1;
		unsigned int LDEN3          : 1;
		unsigned int EIEN3          : 1;
		unsigned int INP3           : 3;
		unsigned int                : 1;
	} B;
	int I;
	unsigned int U;

} SCU_EICR1_type;
#define SCU_EICR1	(*(SCU_EICR1_type*) 0xf0000584u)	/* External Input Channel Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int INTF0          : 1;
		/* const */ unsigned int INTF1          : 1;
		/* const */ unsigned int INTF2          : 1;
		/* const */ unsigned int INTF3          : 1;
		/* const */ unsigned int                : 28;
	} B;
	int I;
	unsigned int U;

} SCU_EIFR_type;
#define SCU_EIFR	(*(SCU_EIFR_type*) 0xf0000588u)	/* External Input Flag Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int POL            : 1;
		unsigned int MODE           : 1;
		unsigned int ENON           : 1;
		unsigned int                : 13;
		/* const */ unsigned int EMSF           : 1;
		unsigned int                : 7;
		unsigned int EMSFM          : 2;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} SCU_EMSR_type;
#define SCU_EMSR	(*(SCU_EMSR_type*) 0xf0000600u)	/* Emergency Stop Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int DFEN           : 1;
		unsigned int                : 2;
		unsigned int EDCON          : 2;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} SCU_ESRCFG0_type;
#define SCU_ESRCFG0	(*(SCU_ESRCFG0_type*) 0xf0000570u)	/* ESR0 Configuration Register  */
#define SCU_ESRCFG1	(*(SCU_ESRCFG0_type*) 0xf0000574u)	/* ESR1 Configuration Register  */
#define SCU_ESRCFG2	(*(SCU_ESRCFG0_type*) 0xf0000578u)	/* ESR2 Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int EN0            : 1;
		unsigned int                : 1;
		unsigned int SEL0           : 4;
		unsigned int GPTAINSEL      : 1;
		unsigned int                : 9;
		unsigned int EN1            : 1;
		unsigned int NSEL           : 1;
		unsigned int SEL1           : 4;
		unsigned int                : 2;
		unsigned int DIV1           : 8;
	} B;
	int I;
	unsigned int U;

} SCU_EXTCON_type;
#define SCU_EXTCON	(*(SCU_EXTCON_type*) 0xf000053cu)	/* External Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STEP           : 10;
		unsigned int                : 4;
		unsigned int DM             : 2;
		/* const */ unsigned int RESULT         : 10;
		unsigned int                : 5;
		unsigned int DISCLK         : 1;
	} B;
	int I;
	unsigned int U;

} SCU_FDR_type;
#define SCU_FDR	(*(SCU_FDR_type*) 0xf0000538u)	/* Fractional Divider Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int FS0            : 1;
		unsigned int FS1            : 1;
		unsigned int FS2            : 1;
		unsigned int FS3            : 1;
		unsigned int                : 12;
		unsigned int FC0            : 1;
		unsigned int FC1            : 1;
		unsigned int FC2            : 1;
		unsigned int FC3            : 1;
		unsigned int                : 12;
	} B;
	int I;
	unsigned int U;

} SCU_FMR_type;
#define SCU_FMR	(*(SCU_FMR_type*) 0xf000058cu)	/* Flag Modification Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MODREV         : 8;
		/* const */ unsigned int MODTYPE        : 8;
		/* const */ unsigned int MODNUMBER      : 16;
	} B;
	int I;
	unsigned int U;

} SCU_ID_type;
#define SCU_ID	(*(SCU_ID_type*) 0xf0000508u)	/* Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int IPEN00         : 1;
		unsigned int IPEN01         : 1;
		unsigned int IPEN02         : 1;
		unsigned int IPEN03         : 1;
		unsigned int                : 9;
		unsigned int GEEN0          : 1;
		unsigned int IGP0           : 2;
		unsigned int IPEN10         : 1;
		unsigned int IPEN11         : 1;
		unsigned int IPEN12         : 1;
		unsigned int IPEN13         : 1;
		unsigned int                : 9;
		unsigned int GEEN1          : 1;
		unsigned int IGP1           : 2;
	} B;
	int I;
	unsigned int U;

} SCU_IGCR0_type;
#define SCU_IGCR0	(*(SCU_IGCR0_type*) 0xf0000594u)	/* Interrupt Gating Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int IPEN20         : 1;
		unsigned int IPEN21         : 1;
		unsigned int IPEN22         : 1;
		unsigned int IPEN23         : 1;
		unsigned int                : 9;
		unsigned int GEEN2          : 1;
		unsigned int IGP2           : 2;
		unsigned int IPEN30         : 1;
		unsigned int IPEN31         : 1;
		unsigned int IPEN32         : 1;
		unsigned int IPEN33         : 1;
		unsigned int                : 9;
		unsigned int GEEN3          : 1;
		unsigned int IGP3           : 2;
	} B;
	int I;
	unsigned int U;

} SCU_IGCR1_type;
#define SCU_IGCR1	(*(SCU_IGCR1_type*) 0xf0000598u)	/* Interrupt Gating Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int P0             : 1;
		/* const */ unsigned int P1             : 1;
		/* const */ unsigned int                : 30;
	} B;
	int I;
	unsigned int U;

} SCU_IN_type;
#define SCU_IN	(*(SCU_IN_type*) 0xf00005acu)	/* Input Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int WDTI           : 1;
		unsigned int ERUI0          : 1;
		unsigned int ERUI1          : 1;
		unsigned int ERUI2          : 1;
		unsigned int ERUI3          : 1;
		unsigned int FL0I           : 1;
		unsigned int                : 1;
		unsigned int DTSI           : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} SCU_INTCLR_type;
#define SCU_INTCLR	(*(SCU_INTCLR_type*) 0xf0000618u)	/* Interrupt Clear Register  */
#define SCU_INTSET	(*(SCU_INTCLR_type*) 0xf0000614u)	/* Interrupt Set Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int WDTI           : 1;
		unsigned int ERUI0          : 1;
		unsigned int ERUI1          : 1;
		unsigned int ERUI2          : 1;
		unsigned int ERUI3          : 1;
		unsigned int FL0I           : 1;
		unsigned int                : 1;
		unsigned int DTSI           : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} SCU_INTDIS_type;
#define SCU_INTDIS	(*(SCU_INTDIS_type*) 0xf000061cu)	/* Interrupt Disable Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int WDT            : 2;
		unsigned int ERU0           : 2;
		unsigned int ERU1           : 2;
		unsigned int ERU2           : 2;
		unsigned int ERU3           : 2;
		unsigned int FL0            : 2;
		unsigned int                : 2;
		unsigned int DTS            : 2;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SCU_INTNP_type;
#define SCU_INTNP	(*(SCU_INTNP_type*) 0xf0000620u)	/* Interrupt Node Pointer Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int WDTI           : 1;
		/* const */ unsigned int ERUI0          : 1;
		/* const */ unsigned int ERUI1          : 1;
		/* const */ unsigned int ERUI2          : 1;
		/* const */ unsigned int ERUI3          : 1;
		/* const */ unsigned int FL0I           : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int DTSI           : 1;
		/* const */ unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} SCU_INTSTAT_type;
#define SCU_INTSTAT	(*(SCU_INTSTAT_type*) 0xf0000610u)	/* Interrupt Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int PC0            : 4;
		unsigned int                : 4;
		unsigned int PC1            : 4;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SCU_IOCR_type;
#define SCU_IOCR	(*(SCU_IOCR_type*) 0xf00005a0u)	/* Input/Output Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int DEPT           : 5;
		/* const */ unsigned int MANUF          : 11;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SCU_MANID_type;
#define SCU_MANID	(*(SCU_MANID_type*) 0xf0000644u)	/* Manufacturer Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PS0            : 1;
		unsigned int PS1            : 1;
		unsigned int                : 14;
		unsigned int PR0            : 1;
		unsigned int PR1            : 1;
		unsigned int                : 14;
	} B;
	int I;
	unsigned int U;

} SCU_OMR_type;
#define SCU_OMR	(*(SCU_OMR_type*) 0xf00005a8u)	/* Output Modification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 1;
		/* const */ unsigned int PLLLV          : 1;
		unsigned int OSCRES         : 1;
		/* const */ unsigned int GAINSEL        : 2;
		unsigned int MODE           : 2;
		unsigned int SHBY           : 1;
		/* const */ unsigned int PLLHV          : 1;
		/* const */ unsigned int PLLSP          : 1;
		/* const */ unsigned int X1D            : 1;
		unsigned int X1DEN          : 1;
		unsigned int                : 4;
		unsigned int OSCVAL         : 5;
		unsigned int                : 11;
	} B;
	int I;
	unsigned int U;

} SCU_OSCCON_type;
#define SCU_OSCCON	(*(SCU_OSCCON_type*) 0xf0000510u)	/* OSC Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int P0             : 1;
		unsigned int P1             : 1;
		unsigned int                : 30;
	} B;
	int I;
	unsigned int U;

} SCU_OUT_type;
#define SCU_OUT	(*(SCU_OUT_type*) 0xf00005a4u)	/* Output Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int PDR0           : 1;
		/* const */ unsigned int PDR1           : 1;
		/* const */ unsigned int PDR2           : 1;
		/* const */ unsigned int PDR3           : 1;
		/* const */ unsigned int                : 28;
	} B;
	int I;
	unsigned int U;

} SCU_PDRR_type;
#define SCU_PDRR	(*(SCU_PDRR_type*) 0xf0000590u)	/* Pattern Detection Result Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int PFLLDRAM       : 1;
		/* const */ unsigned int PFLDTAG        : 1;
		/* const */ unsigned int PFLSPRAM       : 1;
		/* const */ unsigned int PFLPTAG        : 1;
		/* const */ unsigned int PFLPMU         : 1;
		/* const */ unsigned int PFLPRAM        : 1;
		/* const */ unsigned int PFLCMEM        : 1;
		/* const */ unsigned int PFLCAN         : 1;
		/* const */ unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} SCU_PETSR_type;
#define SCU_PETSR	(*(SCU_PETSR_type*) 0xf00005d4u)	/* Parity Error Trap Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int VCOBYP         : 1;
		unsigned int VCOPWD         : 1;
		unsigned int                : 2;
		unsigned int SETFINDIS      : 1;
		unsigned int CLRFINDIS      : 1;
		unsigned int OSCDISCDIS     : 1;
		unsigned int                : 2;
		unsigned int NDIV           : 7;
		unsigned int PLLPWD         : 1;
		unsigned int                : 1;
		unsigned int RESLD          : 1;
		unsigned int                : 5;
		unsigned int PDIV           : 4;
		unsigned int                : 4;
	} B;
	int I;
	unsigned int U;

} SCU_PLLCON0_type;
#define SCU_PLLCON0	(*(SCU_PLLCON0_type*) 0xf0000518u)	/* PLL Configuration 0 Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int K2DIV          : 7;
		unsigned int                : 9;
		unsigned int K1DIV          : 7;
		unsigned int                : 9;
	} B;
	int I;
	unsigned int U;

} SCU_PLLCON1_type;
#define SCU_PLLCON1	(*(SCU_PLLCON1_type*) 0xf000051cu)	/* PLL Configuration 1 Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int VCOBYST        : 1;
		/* const */ unsigned int PWDSTAT        : 1;
		/* const */ unsigned int VCOLOCK        : 1;
		/* const */ unsigned int FINDIS         : 1;
		/* const */ unsigned int K1RDY          : 1;
		/* const */ unsigned int                : 27;
	} B;
	int I;
	unsigned int U;

} SCU_PLLSTAT_type;
#define SCU_PLLSTAT	(*(SCU_PLLSTAT_type*) 0xf0000514u)	/* PLL Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int REQSLP         : 2;
		unsigned int                : 6;
		/* const */ unsigned int PMST           : 3;
		unsigned int                : 21;
	} B;
	int I;
	unsigned int U;

} SCU_PMCSR_type;
#define SCU_PMCSR	(*(SCU_PMCSR_type*) 0xf00005b0u)	/* Power Management Control and Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int RELSA          : 16;
		unsigned int RELD           : 16;
	} B;
	int I;
	unsigned int U;

} SCU_RSTCNTCON_type;
#define SCU_RSTCNTCON	(*(SCU_RSTCNTCON_type*) 0xf0000554u)	/* Reset Counter Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ESR0           : 2;
		unsigned int ESR1           : 2;
		unsigned int                : 2;
		unsigned int WDT            : 2;
		unsigned int SW             : 2;
		unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} SCU_RSTCON_type;
#define SCU_RSTCON	(*(SCU_RSTCON_type*) 0xf0000558u)	/* Reset Configuration Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int ESR0           : 1;
		/* const */ unsigned int ESR1           : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int WDT            : 1;
		/* const */ unsigned int SW             : 1;
		/* const */ unsigned int                : 11;
		/* const */ unsigned int PORST          : 1;
		/* const */ unsigned int OCDS           : 1;
		/* const */ unsigned int CB0            : 1;
		/* const */ unsigned int CB1            : 1;
		/* const */ unsigned int CB3            : 1;
		/* const */ unsigned int TP             : 1;
		/* const */ unsigned int                : 10;
	} B;
	int I;
	unsigned int U;

} SCU_RSTSTAT_type;
#define SCU_RSTSTAT	(*(SCU_RSTSTAT_type*) 0xf0000550u)	/* Reset Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SCU_SRC0_type;
#define SCU_SRC0	(*(SCU_SRC0_type*) 0xf00006fcu)	/* Service Request Control 0 Register  */
#define SCU_SRC1	(*(SCU_SRC0_type*) 0xf00006f8u)	/* Service Request Control 1 Register  */
#define SCU_SRC2	(*(SCU_SRC0_type*) 0xf00006f4u)	/* Service Request Control 2 Register  */
#define SCU_SRC3	(*(SCU_SRC0_type*) 0xf00006f0u)	/* Service Request Control 3 Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int HWCFG          : 8;
		unsigned int                : 5;
		unsigned int SFCBAE         : 1;
		unsigned int CFCBAE         : 1;
		unsigned int STP            : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SCU_STCON_type;
#define SCU_STCON	(*(SCU_STCON_type*) 0xf00005c4u)	/* Start-up Configuration Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int HWCFG          : 8;
		/* const */ unsigned int                : 7;
		/* const */ unsigned int Mode           : 1;
		/* const */ unsigned int FCBAE          : 1;
		/* const */ unsigned int LUDIS          : 1;
		/* const */ unsigned int EXTBEN         : 1;
		/* const */ unsigned int TRSTL          : 1;
		/* const */ unsigned int                : 12;
	} B;
	int I;
	unsigned int U;

} SCU_STSTAT_type;
#define SCU_STSTAT	(*(SCU_STSTAT_type*) 0xf00005c0u)	/* Start-up Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SWBOOT         : 1;
		unsigned int SWRSTREQ       : 1;
		unsigned int                : 6;
		unsigned int SWCFG          : 8;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SCU_SWRSTCON_type;
#define SCU_SWRSTCON	(*(SCU_SWRSTCON_type*) 0xf0000560u)	/* Software Reset Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 2;
		unsigned int GPTAIS         : 2;
		unsigned int SETLUDIS       : 1;
		unsigned int SETEXTBEN      : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} SCU_SYSCON_type;
#define SCU_SYSCON	(*(SCU_SYSCON_type*) 0xf0000540u)	/* System Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ESR0T          : 1;
		unsigned int ESR1T          : 1;
		unsigned int                : 1;
		unsigned int WDTT           : 1;
		unsigned int PET            : 1;
		unsigned int OSCLWDTT       : 1;
		unsigned int OSCHWDTT       : 1;
		unsigned int OSCSPWDTT      : 1;
		unsigned int SYSVCOLCKT     : 1;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} SCU_TRAPCLR_type;
#define SCU_TRAPCLR	(*(SCU_TRAPCLR_type*) 0xf000062cu)	/* Trap Clear Register  */
#define SCU_TRAPSET	(*(SCU_TRAPCLR_type*) 0xf0000628u)	/* Trap Set Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ESR0T          : 1;
		unsigned int ESR1T          : 1;
		unsigned int                : 1;
		unsigned int WDTT           : 1;
		unsigned int PET            : 1;
		unsigned int OSCLWDTT       : 1;
		unsigned int OSCHWDTT       : 1;
		unsigned int OSCSPWDTT      : 1;
		unsigned int SYSVCOLCKT     : 1;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} SCU_TRAPDIS_type;
#define SCU_TRAPDIS	(*(SCU_TRAPDIS_type*) 0xf0000630u)	/* Trap Disable Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int ESR0T          : 1;
		/* const */ unsigned int ESR1T          : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int WDTT           : 1;
		/* const */ unsigned int PET            : 1;
		/* const */ unsigned int OSCLWDTT       : 1;
		/* const */ unsigned int OSCHWDTT       : 1;
		/* const */ unsigned int OSCSPWDTT      : 1;
		/* const */ unsigned int SYSVCOLCKT     : 1;
		/* const */ unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} SCU_TRAPSTAT_type;
#define SCU_TRAPSTAT	(*(SCU_TRAPSTAT_type*) 0xf0000624u)	/* Trap Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ENDINIT        : 1;
		unsigned int LCK            : 1;
		unsigned int HPW0           : 2;
		unsigned int HPW1           : 4;
		unsigned int PW             : 8;
		unsigned int REL            : 16;
	} B;
	int I;
	unsigned int U;

} WDT_CON0_type;
#define WDT_CON0	(*(WDT_CON0_type*) 0xf00005f0u)	/* WDT Control Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int CLRIRF         : 1;
		unsigned int                : 1;
		unsigned int IR             : 1;
		unsigned int DR             : 1;
		unsigned int                : 28;
	} B;
	int I;
	unsigned int U;

} WDT_CON1_type;
#define WDT_CON1	(*(WDT_CON1_type*) 0xf00005f4u)	/* WDT Control Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int AE             : 1;
		/* const */ unsigned int OE             : 1;
		/* const */ unsigned int IS             : 1;
		/* const */ unsigned int DS             : 1;
		/* const */ unsigned int TO             : 1;
		/* const */ unsigned int PR             : 1;
		/* const */ unsigned int                : 10;
		/* const */ unsigned int TIM            : 16;
	} B;
	int I;
	unsigned int U;

} WDT_SR_type;
#define WDT_SR	(*(WDT_SR_type*) 0xf00005f8u)	/* WDT Status Register  */


/* Buses */
typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MOD_REV        : 8;
		/* const */ unsigned int MOD_TYPE       : 8;
		/* const */ unsigned int MOD_NUMBER     : 16;
	} B;
	int I;
	unsigned int U;

} LBCU_ID_type;
#define LBCU_ID	(*(LBCU_ID_type*) 0xf87ffe08u)	/* Module Identification Register  */
#define LFI_ID	(*(LBCU_ID_type*) 0xf87fff08u)	/* Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int LEADDR         : 32;
	} B;
	int I;
	unsigned int U;

} LBCU_LEADDR_type;
#define LBCU_LEADDR	(*(LBCU_LEADDR_type*) 0xf87ffe24u)	/* LBCU LMB Error Address Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 LEC            : 1;
		unsigned __sfrbit32                : 3;
		/* const */ unsigned __sfrbit32 FPITAG         : 4;
		unsigned __sfrbit32                : 6;
		/* const */ unsigned __sfrbit32 NOS            : 1;
		/* const */ unsigned __sfrbit32 LOC            : 1;
		/* const */ unsigned __sfrbit32 ACK            : 3;
		/* const */ unsigned __sfrbit32 UIS            : 1;
		unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 SVM            : 1;
		/* const */ unsigned __sfrbit32 WR             : 1;
		/* const */ unsigned __sfrbit32 RD             : 1;
		/* const */ unsigned __sfrbit32 TAG            : 3;
		unsigned __sfrbit32                : 1;
		/* const */ unsigned __sfrbit32 OPC            : 4;
	} B;
	int I;
	unsigned int U;

} LBCU_LEATT_type;
#define LBCU_LEATT	(*(LBCU_LEATT_type*) 0xf87ffe20u)	/* LBCU LMB Error Attribute Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int LEDAT_63_32_   : 32;
	} B;
	int I;
	unsigned int U;

} LBCU_LEDATH_type;
#define LBCU_LEDATH	(*(LBCU_LEDATH_type*) 0xf87ffe2cu)	/* LBCU LMB Error Data High Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int LEDAT_31_0_    : 32;
	} B;
	int I;
	unsigned int U;

} LBCU_LEDATL_type;
#define LBCU_LEDATL	(*(LBCU_LEDATL_type*) 0xf87ffe28u)	/* LBCU LMB Error Data Low Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 SRPN           : 8;
		unsigned __sfrbit32                : 2;
		/* const */ unsigned __sfrbit32 TOS            : 2;
		unsigned __sfrbit32 SRE            : 1;
		/* const */ unsigned __sfrbit32 SRR            : 1;
		unsigned __sfrbit32 CLRR           : 1;
		unsigned __sfrbit32 SETR           : 1;
		unsigned __sfrbit32                : 16;
	} B;
	int I;
	unsigned int U;

} LBCU_SRC_type;
#define LBCU_SRC	(*(LBCU_SRC_type*) 0xf87ffefcu)	/* LBCU Service Request Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int                : 4;
		/* const */ unsigned int LTAG           : 3;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int FTAG           : 4;
		/* const */ unsigned int                : 20;
	} B;
	int I;
	unsigned int U;

} LFI_CON_type;
#define LFI_CON	(*(LFI_CON_type*) 0xf87fff10u)	/* LFI Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int TOUT           : 16;	/* Bus time-out value */
		unsigned int DBG            : 1;	/* Debug Trace Enable */
		unsigned int                : 2;
		unsigned int SPE            : 1;	/* Starvation Protection Enable */
		unsigned int                : 4;
		unsigned int SPC            : 8;	/* Starvation Period Counter */
	} B;
	int I;
	unsigned int U;

} SBCU_CON_type;
#define SBCU_CON	(*(SBCU_CON_type*) 0xf0000110u)	/* SBCU Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ADR1           : 32;
	} B;
	int I;
	unsigned int U;

} SBCU_DBADR1_type;
#define SBCU_DBADR1	(*(SBCU_DBADR1_type*) 0xf0000138u)	/* SBCU Debug Address 1 Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ADR2           : 32;
	} B;
	int I;
	unsigned int U;

} SBCU_DBADR2_type;
#define SBCU_DBADR2	(*(SBCU_DBADR2_type*) 0xf000013cu)	/* SBCU Debug Address 2 Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int FPIADR         : 32;
	} B;
	int I;
	unsigned int U;

} SBCU_DBADRT_type;
#define SBCU_DBADRT	(*(SBCU_DBADRT_type*) 0xf0000148u)	/* SBCU Debug Trapped Address Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int OPC            : 4;
		unsigned int SVM            : 1;
		unsigned int                : 3;
		unsigned int WR             : 1;
		unsigned int                : 3;
		unsigned int RD             : 1;
		unsigned int                : 19;
	} B;
	int I;
	unsigned int U;

} SBCU_DBBOS_type;
#define SBCU_DBBOS	(*(SBCU_DBBOS_type*) 0xf0000140u)	/* SBCU Debug Bus Operation Signals Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int FPIOPC         : 4;
		/* const */ unsigned int FPISVM         : 1;
		/* const */ unsigned int FPIACK         : 2;
		/* const */ unsigned int FPIRDY         : 1;
		/* const */ unsigned int FPIWR          : 1;
		/* const */ unsigned int FPIRST         : 2;
		/* const */ unsigned int FPIOPS         : 1;
		/* const */ unsigned int FPIRD          : 1;
		/* const */ unsigned int FPIABORT       : 1;
		/* const */ unsigned int FPITOUT        : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int FPITAG         : 4;
		/* const */ unsigned int                : 12;
	} B;
	int I;
	unsigned int U;

} SBCU_DBBOST_type;
#define SBCU_DBBOST	(*(SBCU_DBBOST_type*) 0xf000014cu)	/* SBCU Debug Trapped Bus Operation Signals Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int EO             : 1;
		/* const */ unsigned int OA             : 1;
		unsigned int                : 2;
		unsigned int RA             : 1;
		unsigned int                : 7;
		unsigned int CONCOM0        : 1;
		unsigned int CONCOM1        : 1;
		unsigned int CONCOM2        : 1;
		unsigned int                : 1;
		unsigned int ONG            : 1;
		unsigned int                : 3;
		unsigned int ONA1           : 2;
		unsigned int                : 2;
		unsigned int ONA2           : 2;
		unsigned int                : 2;
		unsigned int ONBOS0         : 1;
		unsigned int ONBOS1         : 1;
		unsigned int ONBOS2         : 1;
		unsigned int ONBOS3         : 1;
	} B;
	int I;
	unsigned int U;

} SBCU_DBCNTL_type;
#define SBCU_DBCNTL	(*(SBCU_DBCNTL_type*) 0xf0000130u)	/* SBCU Debug Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int FPIDATA        : 32;
	} B;
	int I;
	unsigned int U;

} SBCU_DBDAT_type;
#define SBCU_DBDAT	(*(SBCU_DBDAT_type*) 0xf0000150u)	/* SBCU Debug Data Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int DMAH           : 1;
		/* const */ unsigned int ONES           : 2;
		/* const */ unsigned int PCP            : 1;
		/* const */ unsigned int DMAM           : 1;
		/* const */ unsigned int LFI            : 1;
		/* const */ unsigned int DMAL           : 1;
		/* const */ unsigned int ONE            : 9;
		/* const */ unsigned int CHNR00         : 1;
		/* const */ unsigned int CHNR01         : 1;
		/* const */ unsigned int CHNR02         : 1;
		/* const */ unsigned int CHNR03         : 1;
		/* const */ unsigned int CHNR04         : 1;
		/* const */ unsigned int CHNR05         : 1;
		/* const */ unsigned int CHNR06         : 1;
		/* const */ unsigned int CHNR07         : 1;
		/* const */ unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} SBCU_DBGNTT_type;
#define SBCU_DBGNTT	(*(SBCU_DBGNTT_type*) 0xf0000144u)	/* SBCU Debug Trapped Master Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DMAH           : 1;
		unsigned int ONE            : 2;
		unsigned int PCP            : 1;
		unsigned int DMAM           : 1;
		unsigned int LFI            : 1;
		unsigned int DMAL           : 1;
		unsigned int ONES           : 9;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SBCU_DBGRNT_type;
#define SBCU_DBGRNT	(*(SBCU_DBGRNT_type*) 0xf0000134u)	/* SBCU Debug Grant Mask Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int FPIADR         : 32;
	} B;
	int I;
	unsigned int U;

} SBCU_EADD_type;
#define SBCU_EADD	(*(SBCU_EADD_type*) 0xf0000124u)	/* SBCU Error Address Capture Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ERRCNT         : 16;
		unsigned int TOUT           : 1;
		unsigned int RDY            : 1;
		unsigned int ABT            : 1;
		unsigned int ACK            : 2;
		unsigned int SVM            : 1;
		unsigned int WRN            : 1;
		unsigned int RDN            : 1;
		unsigned int TAG            : 4;
		unsigned int OPC            : 4;
	} B;
	int I;
	unsigned int U;

} SBCU_ECON_type;
#define SBCU_ECON	(*(SBCU_ECON_type*) 0xf0000120u)	/* SBCU Error Control Capture Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int FPIDAT         : 32;
	} B;
	int I;
	unsigned int U;

} SBCU_EDAT_type;
#define SBCU_EDAT	(*(SBCU_EDAT_type*) 0xf0000128u)	/* SBCU Error Data Capture Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MOD_REV        : 8;
		/* const */ unsigned int MOD_NUMBER     : 8;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SBCU_ID_type;
#define SBCU_ID	(*(SBCU_ID_type*) 0xf0000108u)	/* Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SBCU_SRC_type;
#define SBCU_SRC	(*(SBCU_SRC_type*) 0xf00001fcu)	/* SBCU Service Request Control Register  */


/* PMU */
typedef volatile union
{
	struct
	{ 
		unsigned int TE             : 1;
		unsigned int                : 1;
		unsigned int ECENCDIS       : 1;
		unsigned int ECDECDIS       : 1;
		unsigned int CONFSE         : 1;
		unsigned int PREFEDIS       : 1;
		unsigned int FSRAME         : 1;
		unsigned int EEAS           : 1;
		unsigned int FSIINTEN       : 1;
		unsigned int FSIINT         : 1;
		unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} FLASH0_CFTEST_type;
#define FLASH0_CFTEST	(*(FLASH0_CFTEST_type*) 0xf8002100u)	/* CPU Flash Test Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int ECCRCode       : 8;
		/* const */ unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} FLASH0_ECCR_type;
#define FLASH0_ECCR	(*(FLASH0_ECCR_type*) 0xf8002108u)	/* ECC Read Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ECCWCode       : 8;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} FLASH0_ECCW_type;
#define FLASH0_ECCW	(*(FLASH0_ECCW_type*) 0xf8002104u)	/* ECC Write Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int WSPFLASH       : 4;
		unsigned int WSECPF         : 1;
		unsigned int                : 3;
		unsigned int WSDFLASH       : 4;
		unsigned int WSECDF         : 1;
		unsigned int IDLE           : 1;
		unsigned int ESLDIS         : 1;
		unsigned int SLEEP_FSD      : 1;
		/* const */ unsigned int RPA            : 1;
		unsigned int DCF            : 1;
		unsigned int DDF            : 1;
		unsigned int                : 1;
		unsigned int DDFDMA         : 1;
		unsigned int DDFPCP         : 1;
		unsigned int                : 2;
		unsigned int VOPERM         : 1;
		unsigned int SQERM          : 1;
		unsigned int PROERM         : 1;
		unsigned int PFSBERM        : 1;
		unsigned int DFSBERM        : 1;
		unsigned int PFDBERM        : 1;
		unsigned int DFDBERM        : 1;
		unsigned int EOBM           : 1;
	} B;
	int I;
	unsigned int U;

} FLASH0_FCON_type;
#define FLASH0_FCON	(*(FLASH0_FCON_type*) 0xf8002014u)	/* Flash Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PFSIZE         : 8;
		unsigned int DFSIZE         : 5;
		unsigned int                : 19;
	} B;
	int I;
	unsigned int U;

} FLASH0_FSCON_type;
#define FLASH0_FSCON	(*(FLASH0_FSCON_type*) 0xf800210cu)	/* Flash Size Configuration Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int PBUSY          : 1;
		/* const */ unsigned int FABUSY         : 1;
		/* const */ unsigned int D0BUSY         : 1;
		/* const */ unsigned int D1BUSY         : 1;
		/* const */ unsigned int PROG           : 1;
		/* const */ unsigned int ERASE          : 1;
		/* const */ unsigned int PFPAGE         : 1;
		/* const */ unsigned int DFPAGE         : 1;
		/* const */ unsigned int PFOPER         : 1;
		/* const */ unsigned int DFOPER         : 1;
		/* const */ unsigned int SQER           : 1;
		/* const */ unsigned int PROER          : 1;
		/* const */ unsigned int PFSBER         : 1;
		/* const */ unsigned int DFSBER         : 1;
		/* const */ unsigned int PFDBER         : 1;
		/* const */ unsigned int DFDBER         : 1;
		/* const */ unsigned int PROIN          : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int RPROIN         : 1;
		/* const */ unsigned int RPRODIS        : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int WPROIN0        : 1;
		/* const */ unsigned int WPROIN1        : 1;
		/* const */ unsigned int WPROIN2        : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int WPRODIS0       : 1;
		/* const */ unsigned int WPRODIS1       : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int SLM            : 1;
		/* const */ unsigned int VIS            : 1;
		/* const */ unsigned int ORIER          : 1;
		/* const */ unsigned int VER            : 1;
	} B;
	int I;
	unsigned int U;

} FLASH0_FSR_type;
#define FLASH0_FSR	(*(FLASH0_FSR_type*) 0xf8002010u)	/* Flash Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MOD_REV        : 8;
		/* const */ unsigned int MOD_TYPE       : 8;
		/* const */ unsigned int MOD_NUMBER     : 16;
	} B;
	int I;
	unsigned int U;

} FLASH0_ID_type;
#define FLASH0_ID	(*(FLASH0_ID_type*) 0xf8002008u)	/* Flash Module Identification Register  */
#define PMU0_ID	(*(FLASH0_ID_type*) 0xf8000508u)	/* PMU0 Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MARGIN0        : 2;
		unsigned int MARGIN1        : 2;
		unsigned int BNKSEL         : 1;
		unsigned int                : 10;
		unsigned int NaNTRAPDIS     : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} FLASH0_MARD_type;
#define FLASH0_MARD	(*(FLASH0_MARD_type*) 0xf800201cu)	/* Margin Control Register DFLASH  */

typedef volatile union
{
	struct
	{ 
		unsigned int MARGIN0        : 2;
		unsigned int MARGIN1        : 2;
		unsigned int                : 11;
		unsigned int NaNTRAPDIS     : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} FLASH0_MARP_type;
#define FLASH0_MARP	(*(FLASH0_MARP_type*) 0xf8002018u)	/* Margin Control Register PFLASH  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int S0L            : 1;
		/* const */ unsigned int S1L            : 1;
		/* const */ unsigned int S2L            : 1;
		/* const */ unsigned int S3L            : 1;
		/* const */ unsigned int S4L            : 1;
		/* const */ unsigned int S5L            : 1;
		/* const */ unsigned int S6L            : 1;
		/* const */ unsigned int S7L            : 1;
		/* const */ unsigned int S8L            : 1;
		/* const */ unsigned int S9L            : 1;
		/* const */ unsigned int S10_S11L       : 1;
		/* const */ unsigned int S12_S13L       : 1;
		/* const */ unsigned int S14_S15L       : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int DFEXPRO        : 1;
		/* const */ unsigned int RPRO           : 1;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} FLASH0_PROCON0_type;
#define FLASH0_PROCON0	(*(FLASH0_PROCON0_type*) 0xf8002020u)	/* Flash Protection Configuration Register User 0  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int S0L            : 1;
		/* const */ unsigned int S1L            : 1;
		/* const */ unsigned int S2L            : 1;
		/* const */ unsigned int S3L            : 1;
		/* const */ unsigned int S4L            : 1;
		/* const */ unsigned int S5L            : 1;
		/* const */ unsigned int S6L            : 1;
		/* const */ unsigned int S7L            : 1;
		/* const */ unsigned int S8L            : 1;
		/* const */ unsigned int S9L            : 1;
		/* const */ unsigned int S10_S11L       : 1;
		/* const */ unsigned int S12_S13L       : 1;
		/* const */ unsigned int S14_S15L       : 1;
		/* const */ unsigned int                : 19;
	} B;
	int I;
	unsigned int U;

} FLASH0_PROCON1_type;
#define FLASH0_PROCON1	(*(FLASH0_PROCON1_type*) 0xf8002024u)	/* Flash Protection Configuration Register User 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int S0ROM          : 1;
		/* const */ unsigned int S1ROM          : 1;
		/* const */ unsigned int S2ROM          : 1;
		/* const */ unsigned int S3ROM          : 1;
		/* const */ unsigned int S4ROM          : 1;
		/* const */ unsigned int S5ROM          : 1;
		/* const */ unsigned int S6ROM          : 1;
		/* const */ unsigned int S7ROM          : 1;
		/* const */ unsigned int S8ROM          : 1;
		/* const */ unsigned int S9ROM          : 1;
		/* const */ unsigned int S10_S11ROM     : 1;
		/* const */ unsigned int S12_S13ROM     : 1;
		/* const */ unsigned int S14_S15ROM     : 1;
		/* const */ unsigned int                : 2;
		/* const */ unsigned int TP             : 1;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} FLASH0_PROCON2_type;
#define FLASH0_PROCON2	(*(FLASH0_PROCON2_type*) 0xf8002028u)	/* Flash Protection Configuration Register User 2  */

typedef volatile union
{
	struct
	{ 
		unsigned int OLDAEN         : 1;
		unsigned int POLDAEN        : 1;
		unsigned int                : 6;
		unsigned int PPERCTR        : 1;
		unsigned int PEREN          : 1;
		unsigned int PB0W           : 1;
		unsigned int PB1W           : 1;
		/* const */ unsigned int PB0R           : 1;
		/* const */ unsigned int PB1R           : 1;
		unsigned int PB0ERR         : 1;
		unsigned int PB1ERR         : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} PMU0_OVRCON_type;
#define PMU0_OVRCON	(*(PMU0_OVRCON_type*) 0xf8000520u)	/* Overlay RAM Control Register  */


/* OVC */
typedef volatile union
{
	struct
	{ 
		unsigned int SHOVEN0        : 1;
		unsigned int SHOVEN1        : 1;
		unsigned int SHOVEN2        : 1;
		unsigned int SHOVEN3        : 1;
		unsigned int SHOVEN4        : 1;
		unsigned int SHOVEN5        : 1;
		unsigned int SHOVEN6        : 1;
		unsigned int SHOVEN7        : 1;
		unsigned int SHOVEN8        : 1;
		unsigned int SHOVEN9        : 1;
		unsigned int SHOVEN10       : 1;
		unsigned int SHOVEN11       : 1;
		unsigned int SHOVEN12       : 1;
		unsigned int SHOVEN13       : 1;
		unsigned int SHOVEN14       : 1;
		unsigned int SHOVEN15       : 1;
		unsigned int OVSTRT         : 1;
		unsigned int OVSTP          : 1;
		unsigned int DCINVAL        : 1;
		unsigned int                : 5;
		unsigned int OVCONF         : 1;
		unsigned int POVCONF        : 1;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} OVC_OCON_type;
#define OVC_OCON	(*(OVC_OCON_type*) 0xf87ffbe0u)	/* Overlay Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int OMASK          : 7;
		/* const */ unsigned int ONE            : 17;
		unsigned int                : 4;
	} B1;
	struct
	{ 
		unsigned int                : 10;
		unsigned int OMASK          : 7;
		/* const */ unsigned int ONE            : 11;
		unsigned int                : 4;
	} B2;
	int I;
	unsigned int U;

} OVC_OMASK0_type;
#define OVC_OMASK0	(*(OVC_OMASK0_type*) 0xf87ffb28u)	/* Overlay Mask Register 0  */
#define OVC_OMASK1	(*(OVC_OMASK0_type*) 0xf87ffb34u)	/* Overlay Mask Register 1  */
#define OVC_OMASK10	(*(OVC_OMASK0_type*) 0xf87ffba0u)	/* Overlay Mask Register 10  */
#define OVC_OMASK11	(*(OVC_OMASK0_type*) 0xf87ffbacu)	/* Overlay Mask Register 11  */
#define OVC_OMASK12	(*(OVC_OMASK0_type*) 0xf87ffbb8u)	/* Overlay Mask Register 12  */
#define OVC_OMASK13	(*(OVC_OMASK0_type*) 0xf87ffbc4u)	/* Overlay Mask Register 13  */
#define OVC_OMASK14	(*(OVC_OMASK0_type*) 0xf87ffbd0u)	/* Overlay Mask Register 14  */
#define OVC_OMASK15	(*(OVC_OMASK0_type*) 0xf87ffbdcu)	/* Overlay Mask Register 15  */
#define OVC_OMASK2	(*(OVC_OMASK0_type*) 0xf87ffb40u)	/* Overlay Mask Register 2  */
#define OVC_OMASK3	(*(OVC_OMASK0_type*) 0xf87ffb4cu)	/* Overlay Mask Register 3  */
#define OVC_OMASK4	(*(OVC_OMASK0_type*) 0xf87ffb58u)	/* Overlay Mask Register 4  */
#define OVC_OMASK5	(*(OVC_OMASK0_type*) 0xf87ffb64u)	/* Overlay Mask Register 5  */
#define OVC_OMASK6	(*(OVC_OMASK0_type*) 0xf87ffb70u)	/* Overlay Mask Register 6  */
#define OVC_OMASK7	(*(OVC_OMASK0_type*) 0xf87ffb7cu)	/* Overlay Mask Register 7  */
#define OVC_OMASK8	(*(OVC_OMASK0_type*) 0xf87ffb88u)	/* Overlay Mask Register 8  */
#define OVC_OMASK9	(*(OVC_OMASK0_type*) 0xf87ffb94u)	/* Overlay Mask Register 9  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int TBASE          : 24;
		unsigned int TSEG           : 4;
	} B1;
	struct
	{ 
		unsigned int                : 10;
		unsigned int TBASE          : 18;
		unsigned int TSEG           : 4;
	} B2;
	int I;
	unsigned int U;

} OVC_OTAR0_type;
#define OVC_OTAR0	(*(OVC_OTAR0_type*) 0xf87ffb24u)	/* Overlay Target Address Register 0  */
#define OVC_OTAR1	(*(OVC_OTAR0_type*) 0xf87ffb30u)	/* Overlay Target Address Register 1  */
#define OVC_OTAR10	(*(OVC_OTAR0_type*) 0xf87ffb9cu)	/* Overlay Target Address Register 10  */
#define OVC_OTAR11	(*(OVC_OTAR0_type*) 0xf87ffba8u)	/* Overlay Target Address Register 11  */
#define OVC_OTAR12	(*(OVC_OTAR0_type*) 0xf87ffbb4u)	/* Overlay Target Address Register 12  */
#define OVC_OTAR13	(*(OVC_OTAR0_type*) 0xf87ffbc0u)	/* Overlay Target Address Register 13  */
#define OVC_OTAR14	(*(OVC_OTAR0_type*) 0xf87ffbccu)	/* Overlay Target Address Register 14  */
#define OVC_OTAR15	(*(OVC_OTAR0_type*) 0xf87ffbd8u)	/* Overlay Target Address Register 15  */
#define OVC_OTAR2	(*(OVC_OTAR0_type*) 0xf87ffb3cu)	/* Overlay Target Address Register 2  */
#define OVC_OTAR3	(*(OVC_OTAR0_type*) 0xf87ffb48u)	/* Overlay Target Address Register 3  */
#define OVC_OTAR4	(*(OVC_OTAR0_type*) 0xf87ffb54u)	/* Overlay Target Address Register 4  */
#define OVC_OTAR5	(*(OVC_OTAR0_type*) 0xf87ffb60u)	/* Overlay Target Address Register 5  */
#define OVC_OTAR6	(*(OVC_OTAR0_type*) 0xf87ffb6cu)	/* Overlay Target Address Register 6  */
#define OVC_OTAR7	(*(OVC_OTAR0_type*) 0xf87ffb78u)	/* Overlay Target Address Register 7  */
#define OVC_OTAR8	(*(OVC_OTAR0_type*) 0xf87ffb84u)	/* Overlay Target Address Register 8  */
#define OVC_OTAR9	(*(OVC_OTAR0_type*) 0xf87ffb90u)	/* Overlay Target Address Register 9  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int OBASE          : 9;
		unsigned int                : 3;
		/* const */ unsigned int FIXVAL         : 12;
		/* const */ unsigned int RC0            : 1;
		unsigned int EXOMS          : 1;
		unsigned int IEMS           : 1;
		unsigned int OVEN           : 1;
	} B1;
	struct
	{ 
		unsigned int                : 10;
		unsigned int OBASE          : 9;
		unsigned int                : 1;
		/* const */ unsigned int FIXVAL         : 8;
		/* const */ unsigned int RC0            : 1;
		unsigned int EXOMS          : 1;
		unsigned int IEMS           : 1;
		unsigned int OVEN           : 1;
	} B2;
	struct
	{ 
		unsigned int                : 10;
		unsigned int OBASE          : 13;
		/* const */ unsigned int FIXVAL         : 5;
		/* const */ unsigned int RC0            : 1;
		unsigned int EXOMS          : 1;
		unsigned int IEMS           : 1;
		unsigned int OVEN           : 1;
	} B3;
	int I;
	unsigned int U;

} OVC_RABR0_type;
#define OVC_RABR0	(*(OVC_RABR0_type*) 0xf87ffb20u)	/* Redirected Address Base Register 0  */
#define OVC_RABR1	(*(OVC_RABR0_type*) 0xf87ffb2cu)	/* Redirected Address Base Register 1  */
#define OVC_RABR10	(*(OVC_RABR0_type*) 0xf87ffb98u)	/* Redirected Address Base Register 10  */
#define OVC_RABR11	(*(OVC_RABR0_type*) 0xf87ffba4u)	/* Redirected Address Base Register 11  */
#define OVC_RABR12	(*(OVC_RABR0_type*) 0xf87ffbb0u)	/* Redirected Address Base Register 12  */
#define OVC_RABR13	(*(OVC_RABR0_type*) 0xf87ffbbcu)	/* Redirected Address Base Register 13  */
#define OVC_RABR14	(*(OVC_RABR0_type*) 0xf87ffbc8u)	/* Redirected Address Base Register 14  */
#define OVC_RABR15	(*(OVC_RABR0_type*) 0xf87ffbd4u)	/* Redirected Address Base Register 15  */
#define OVC_RABR2	(*(OVC_RABR0_type*) 0xf87ffb38u)	/* Redirected Address Base Register 2  */
#define OVC_RABR3	(*(OVC_RABR0_type*) 0xf87ffb44u)	/* Redirected Address Base Register 3  */
#define OVC_RABR4	(*(OVC_RABR0_type*) 0xf87ffb50u)	/* Redirected Address Base Register 4  */
#define OVC_RABR5	(*(OVC_RABR0_type*) 0xf87ffb5cu)	/* Redirected Address Base Register 5  */
#define OVC_RABR6	(*(OVC_RABR0_type*) 0xf87ffb68u)	/* Redirected Address Base Register 6  */
#define OVC_RABR7	(*(OVC_RABR0_type*) 0xf87ffb74u)	/* Redirected Address Base Register 7  */
#define OVC_RABR8	(*(OVC_RABR0_type*) 0xf87ffb80u)	/* Redirected Address Base Register 8  */
#define OVC_RABR9	(*(OVC_RABR0_type*) 0xf87ffb8cu)	/* Redirected Address Base Register 9  */


/* Ports */
typedef volatile union
{
	struct
	{ 
		unsigned int EN0            : 1;
		unsigned int EN1            : 1;
		unsigned int EN2            : 1;
		unsigned int EN3            : 1;
		unsigned int EN4            : 1;
		unsigned int EN5            : 1;
		unsigned int EN6            : 1;
		unsigned int EN7            : 1;
		unsigned int EN8            : 1;
		unsigned int EN9            : 1;
		unsigned int EN10           : 1;
		unsigned int EN11           : 1;
		unsigned int EN12           : 1;
		unsigned int EN13           : 1;
		unsigned int EN14           : 1;
		unsigned int EN15           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} P0_ESR_type;
#define P0_ESR	(*(P0_ESR_type*) 0xf0000c50u)	/* Port 0 Emergency Stop Register  */
#define P1_ESR	(*(P0_ESR_type*) 0xf0000d50u)	/* Port 1 Emergency Stop Register  */
#define P2_ESR	(*(P0_ESR_type*) 0xf0000e50u)	/* Port 2 Emergency Stop Register  */
#define P3_ESR	(*(P0_ESR_type*) 0xf0000f50u)	/* Port 3 Emergency Stop Register  */
#define P4_ESR	(*(P0_ESR_type*) 0xf0001050u)	/* Port 4 Emergency Stop Register  */
#define P5_ESR	(*(P0_ESR_type*) 0xf0001150u)	/* Port 5 Emergency Stop Register  */
#define P6_ESR	(*(P0_ESR_type*) 0xf0001250u)	/* Port 6 Emergency Stop Register  */
#define P7_ESR	(*(P0_ESR_type*) 0xf0001350u)	/* Port 7 Emergency Stop Register  */
#define P8_ESR	(*(P0_ESR_type*) 0xf0001450u)	/* Port 8 Emergency Stop Register  */
#define P9_ESR	(*(P0_ESR_type*) 0xf0001550u)	/* Port 9 Emergency Stop Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int P0             : 1;
		/* const */ unsigned int P1             : 1;
		/* const */ unsigned int P2             : 1;
		/* const */ unsigned int P3             : 1;
		/* const */ unsigned int P4             : 1;
		/* const */ unsigned int P5             : 1;
		/* const */ unsigned int P6             : 1;
		/* const */ unsigned int P7             : 1;
		/* const */ unsigned int P8             : 1;
		/* const */ unsigned int P9             : 1;
		/* const */ unsigned int P10            : 1;
		/* const */ unsigned int P11            : 1;
		/* const */ unsigned int P12            : 1;
		/* const */ unsigned int P13            : 1;
		/* const */ unsigned int P14            : 1;
		/* const */ unsigned int P15            : 1;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} P0_IN_type;
#define P0_IN	(*(P0_IN_type*) 0xf0000c24u)	/* Port 0 Input Register  */
#define P1_IN	(*(P0_IN_type*) 0xf0000d24u)	/* Port 1 Input Register  */
#define P2_IN	(*(P0_IN_type*) 0xf0000e24u)	/* Port 2 Input Register  */
#define P3_IN	(*(P0_IN_type*) 0xf0000f24u)	/* Port 3 Input Register  */
#define P4_IN	(*(P0_IN_type*) 0xf0001024u)	/* Port 4 Input Register  */
#define P5_IN	(*(P0_IN_type*) 0xf0001124u)	/* Port 5 Input Register  */
#define P6_IN	(*(P0_IN_type*) 0xf0001224u)	/* Port 6 Input Register  */
#define P7_IN	(*(P0_IN_type*) 0xf0001324u)	/* Port 7 Input Register  */
#define P8_IN	(*(P0_IN_type*) 0xf0001424u)	/* Port 8 Input Register  */
#define P9_IN	(*(P0_IN_type*) 0xf0001524u)	/* Port 9 Input Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int PC0            : 4;
		unsigned int                : 4;
		unsigned int PC1            : 4;
		unsigned int                : 4;
		unsigned int PC2            : 4;
		unsigned int                : 4;
		unsigned int PC3            : 4;
	} B;
	int I;
	unsigned int U;

} P0_IOCR0_type;
#define P0_IOCR0	(*(P0_IOCR0_type*) 0xf0000c10u)	/* Port 0 Input/Output Control Register 0  */
#define P1_IOCR0	(*(P0_IOCR0_type*) 0xf0000d10u)	/* Port 1 Input/Output Control Register 0  */
#define P2_IOCR0	(*(P0_IOCR0_type*) 0xf0000e10u)	/* Port 2 Input/Output Control Register 0  */
#define P3_IOCR0	(*(P0_IOCR0_type*) 0xf0000f10u)	/* Port 3 Input/Output Control Register 0  */
#define P4_IOCR0	(*(P0_IOCR0_type*) 0xf0001010u)	/* Port 4 Input/Output Control Register 0  */
#define P5_IOCR0	(*(P0_IOCR0_type*) 0xf0001110u)	/* Port 5 Input/Output Control Register 0  */
#define P6_IOCR0	(*(P0_IOCR0_type*) 0xf0001210u)	/* Port 6 Input/Output Control Register 0  */
#define P7_IOCR0	(*(P0_IOCR0_type*) 0xf0001310u)	/* Port 7 Input/Output Control Register 0  */
#define P8_IOCR0	(*(P0_IOCR0_type*) 0xf0001410u)	/* Port 8 Input/Output Control Register 0  */
#define P9_IOCR0	(*(P0_IOCR0_type*) 0xf0001510u)	/* Port 9 Input/Output Control Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int PC12           : 4;
		unsigned int                : 4;
		unsigned int PC13           : 4;
		unsigned int                : 4;
		unsigned int PC14           : 4;
		unsigned int                : 4;
		unsigned int PC15           : 4;
	} B;
	int I;
	unsigned int U;

} P0_IOCR12_type;
#define P0_IOCR12	(*(P0_IOCR12_type*) 0xf0000c1cu)	/* Port 0 Input/Output Control Register 12  */
#define P1_IOCR12	(*(P0_IOCR12_type*) 0xf0000d1cu)	/* Port 1 Input/Output Control Register 12  */
#define P2_IOCR12	(*(P0_IOCR12_type*) 0xf0000e1cu)	/* Port 2 Input/Output Control Register 12  */
#define P3_IOCR12	(*(P0_IOCR12_type*) 0xf0000f1cu)	/* Port 3 Input/Output Control Register 12  */
#define P5_IOCR12	(*(P0_IOCR12_type*) 0xf000111cu)	/* Port 5 Input/Output Control Register 12  */
#define P7_IOCR12	(*(P0_IOCR12_type*) 0xf000131cu)	/* Port 7 Input/Output Control Register 12  */
#define P8_IOCR12	(*(P0_IOCR12_type*) 0xf000141cu)	/* Port 8 Input/Output Control Register 12  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int PC4            : 4;
		unsigned int                : 4;
		unsigned int PC5            : 4;
		unsigned int                : 4;
		unsigned int PC6            : 4;
		unsigned int                : 4;
		unsigned int PC7            : 4;
	} B;
	int I;
	unsigned int U;

} P0_IOCR4_type;
#define P0_IOCR4	(*(P0_IOCR4_type*) 0xf0000c14u)	/* Port 0 Input/Output Control Register 4  */
#define P1_IOCR4	(*(P0_IOCR4_type*) 0xf0000d14u)	/* Port 1 Input/Output Control Register 4  */
#define P2_IOCR4	(*(P0_IOCR4_type*) 0xf0000e14u)	/* Port 2 Input/Output Control Register 4  */
#define P3_IOCR4	(*(P0_IOCR4_type*) 0xf0000f14u)	/* Port 3 Input/Output Control Register 4  */
#define P5_IOCR4	(*(P0_IOCR4_type*) 0xf0001114u)	/* Port n Input/Output Control Register 4  */
#define P7_IOCR4	(*(P0_IOCR4_type*) 0xf0001314u)	/* Port 7 Input/Output Control Register 4  */
#define P8_IOCR4	(*(P0_IOCR4_type*) 0xf0001414u)	/* Port 8 Input/Output Control Register 4  */
#define P9_IOCR4	(*(P0_IOCR4_type*) 0xf0001514u)	/* Port 9 Input/Output Control Register 4  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int PC8            : 4;
		unsigned int                : 4;
		unsigned int PC9            : 4;
		unsigned int                : 4;
		unsigned int PC10           : 4;
		unsigned int                : 4;
		unsigned int PC11           : 4;
	} B;
	int I;
	unsigned int U;

} P0_IOCR8_type;
#define P0_IOCR8	(*(P0_IOCR8_type*) 0xf0000c18u)	/* Port 0 Input/Output Control Register 8  */
#define P1_IOCR8	(*(P0_IOCR8_type*) 0xf0000d18u)	/* Port 1 Input/Output Control Register 8  */
#define P2_IOCR8	(*(P0_IOCR8_type*) 0xf0000e18u)	/* Port 2 Input/Output Control Register 8  */
#define P3_IOCR8	(*(P0_IOCR8_type*) 0xf0000f18u)	/* Port 3 Input/Output Control Register 8  */
#define P5_IOCR8	(*(P0_IOCR8_type*) 0xf0001118u)	/* Port n Input/Output Control Register 8  */
#define P7_IOCR8	(*(P0_IOCR8_type*) 0xf0001318u)	/* Port 7 Input/Output Control Register 8  */
#define P8_IOCR8	(*(P0_IOCR8_type*) 0xf0001418u)	/* Port 8 Input/Output Control Register 8  */
#define P9_IOCR8	(*(P0_IOCR8_type*) 0xf0001518u)	/* Port 9 Input/Output Control Register 8  */

typedef volatile union
{
	struct
	{ 
		unsigned int PS0            : 1;
		unsigned int PS1            : 1;
		unsigned int PS2            : 1;
		unsigned int PS3            : 1;
		unsigned int PS4            : 1;
		unsigned int PS5            : 1;
		unsigned int PS6            : 1;
		unsigned int PS7            : 1;
		unsigned int PS8            : 1;
		unsigned int PS9            : 1;
		unsigned int PS10           : 1;
		unsigned int PS11           : 1;
		unsigned int PS12           : 1;
		unsigned int PS13           : 1;
		unsigned int PS14           : 1;
		unsigned int PS15           : 1;
		unsigned int PR0            : 1;
		unsigned int PR1            : 1;
		unsigned int PR2            : 1;
		unsigned int PR3            : 1;
		unsigned int PR4            : 1;
		unsigned int PR5            : 1;
		unsigned int PR6            : 1;
		unsigned int PR7            : 1;
		unsigned int PR8            : 1;
		unsigned int PR9            : 1;
		unsigned int PR10           : 1;
		unsigned int PR11           : 1;
		unsigned int PR12           : 1;
		unsigned int PR13           : 1;
		unsigned int PR14           : 1;
		unsigned int PR15           : 1;
	} B;
	int I;
	unsigned int U;

} P0_OMR_type;
#define P0_OMR	(*(P0_OMR_type*) 0xf0000c04u)	/* Port 0 Output Modification Register  */
#define P1_OMR	(*(P0_OMR_type*) 0xf0000d04u)	/* Port 1 Output Modification Register  */
#define P2_OMR	(*(P0_OMR_type*) 0xf0000e04u)	/* Port 2 Output Modification Register  */
#define P3_OMR	(*(P0_OMR_type*) 0xf0000f04u)	/* Port 3 Output Modification Register  */
#define P4_OMR	(*(P0_OMR_type*) 0xf0001004u)	/* Port 4 Output Modification Register  */
#define P5_OMR	(*(P0_OMR_type*) 0xf0001104u)	/* Port 5 Output Modification Register  */
#define P6_OMR	(*(P0_OMR_type*) 0xf0001204u)	/* Port 6 Output Modification Register  */
#define P7_OMR	(*(P0_OMR_type*) 0xf0001304u)	/* Port 7 Output Modification Register  */
#define P8_OMR	(*(P0_OMR_type*) 0xf0001404u)	/* Port 8 Output Modification Register  */
#define P9_OMR	(*(P0_OMR_type*) 0xf0001504u)	/* Port 9 Output Modification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int P0             : 1;
		unsigned int P1             : 1;
		unsigned int P2             : 1;
		unsigned int P3             : 1;
		unsigned int P4             : 1;
		unsigned int P5             : 1;
		unsigned int P6             : 1;
		unsigned int P7             : 1;
		unsigned int P8             : 1;
		unsigned int P9             : 1;
		unsigned int P10            : 1;
		unsigned int P11            : 1;
		unsigned int P12            : 1;
		unsigned int P13            : 1;
		unsigned int P14            : 1;
		unsigned int P15            : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} P0_OUT_type;
#define P0_OUT	(*(P0_OUT_type*) 0xf0000c00u)	/* Port 0 Output Register  */
#define P1_OUT	(*(P0_OUT_type*) 0xf0000d00u)	/* Port 1 Output Register  */
#define P2_OUT	(*(P0_OUT_type*) 0xf0000e00u)	/* Port 2 Output Register  */
#define P3_OUT	(*(P0_OUT_type*) 0xf0000f00u)	/* Port 3 Output Register  */
#define P4_OUT	(*(P0_OUT_type*) 0xf0001000u)	/* Port 4 Output Register  */
#define P5_OUT	(*(P0_OUT_type*) 0xf0001100u)	/* Port 5 Output Register  */
#define P6_OUT	(*(P0_OUT_type*) 0xf0001200u)	/* Port 6 Output Register  */
#define P7_OUT	(*(P0_OUT_type*) 0xf0001300u)	/* Port 7 Output Register  */
#define P8_OUT	(*(P0_OUT_type*) 0xf0001400u)	/* Port 8 Output Register  */
#define P9_OUT	(*(P0_OUT_type*) 0xf0001500u)	/* Port 9 Output Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PD1            : 3;
		unsigned int                : 25;
	} B;
	int I;
	unsigned int U;

} P0_PDR_type;
#define P0_PDR	(*(P0_PDR_type*) 0xf0000c40u)	/* Port 0 Pad Driver Mode Register  */
#define P6_PDR	(*(P0_PDR_type*) 0xf0001240u)	/* Port 6 Pad Driver Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PD1            : 3;
		unsigned int                : 1;
		unsigned int PDEMUX         : 3;
		unsigned int                : 1;
		unsigned int PD2            : 3;
		unsigned int                : 1;
		unsigned int PDSSC1B        : 3;
		unsigned int                : 1;
		unsigned int PDBRKOUT0      : 3;
		unsigned int                : 9;
	} B;
	int I;
	unsigned int U;

} P1_PDR_type;
#define P1_PDR	(*(P1_PDR_type*) 0xf0000d40u)	/* Port 1 Pad Driver Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PD1            : 3;
		unsigned int                : 9;
		unsigned int PDMLI0         : 3;
		unsigned int                : 1;
		unsigned int PDMSC0         : 3;
		unsigned int                : 1;
		unsigned int PDSSC1         : 3;
		unsigned int                : 5;
	} B;
	int I;
	unsigned int U;

} P2_PDR_type;
#define P2_PDR	(*(P2_PDR_type*) 0xf0000e40u)	/* Port 2 Pad Driver Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PD1            : 3;
		unsigned int                : 9;
		unsigned int PDASC0         : 3;
		unsigned int                : 1;
		unsigned int PDSSC0         : 3;
		unsigned int                : 1;
		unsigned int PDASC1         : 3;
		unsigned int                : 1;
		unsigned int PDCAN          : 3;
		unsigned int                : 1;
	} B;
	int I;
	unsigned int U;

} P3_PDR_type;
#define P3_PDR	(*(P3_PDR_type*) 0xf0000f40u)	/* Port 3 Pad Driver Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PDEXTCLK1      : 3;
		unsigned int                : 9;
		unsigned int PDEXTCLK0      : 3;
		unsigned int                : 13;
	} B;
	int I;
	unsigned int U;

} P4_PDR_type;
#define P4_PDR	(*(P4_PDR_type*) 0xf0001040u)	/* Port 4 Pad Driver Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PD1            : 3;
		unsigned int                : 1;
		unsigned int PD2            : 3;
		unsigned int                : 5;
		unsigned int PDMLI0         : 3;
		unsigned int                : 13;
	} B;
	int I;
	unsigned int U;

} P5_PDR_type;
#define P5_PDR	(*(P5_PDR_type*) 0xf0001140u)	/* Port 5 Pad Driver Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PD1            : 3;
		unsigned int                : 1;
		unsigned int PD2            : 3;
		unsigned int                : 1;
		unsigned int PD3            : 3;
		unsigned int                : 17;
	} B;
	int I;
	unsigned int U;

} P7_PDR_type;
#define P7_PDR	(*(P7_PDR_type*) 0xf0001340u)	/* Port 7 Pad Driver Mode Register  */
#define P8_PDR	(*(P7_PDR_type*) 0xf0001440u)	/* Port 8 Pad Driver Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PD0            : 3;
		unsigned int                : 1;
		unsigned int PD1            : 3;
		unsigned int                : 9;
		unsigned int PDCAN          : 3;
		unsigned int                : 13;
	} B;
	int I;
	unsigned int U;

} P9_PDR_type;
#define P9_PDR	(*(P9_PDR_type*) 0xf0001540u)	/* Port 9 Pad Driver Mode Register  */


/* PCP */
typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32                : 15;
		unsigned __sfrbit32 PCGDIS         : 1;
		unsigned __sfrbit32                : 16;
	} B;
	int I;
	unsigned int U;

} PCP_CLC_type;
#define PCP_CLC	(*(PCP_CLC_type*) 0xf0043f00u)	/* PCP Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 EN             : 1;
		unsigned __sfrbit32 RST            : 1;
		/* const */ unsigned __sfrbit32 RS             : 1;
		unsigned __sfrbit32                : 1;
		unsigned __sfrbit32 RCB            : 1;
		unsigned __sfrbit32 EIE            : 1;
		unsigned __sfrbit32 CS             : 2;
		unsigned __sfrbit32 PPE            : 1;
		unsigned __sfrbit32 PPS            : 7;
		unsigned __sfrbit32 CWE            : 1;
		unsigned __sfrbit32 CWT            : 7;
		unsigned __sfrbit32 ESR            : 8;
	} B;
	int I;
	unsigned int U;

} PCP_CS_type;
#define PCP_CS	(*(PCP_CS_type*) 0xf0043f10u)	/* PCP Control/Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 BER            : 1;
		/* const */ unsigned __sfrbit32 IOP            : 1;
		/* const */ unsigned __sfrbit32 DCR            : 1;
		/* const */ unsigned __sfrbit32 IAE            : 1;
		/* const */ unsigned __sfrbit32 DBE            : 1;
		/* const */ unsigned __sfrbit32 ME             : 1;
		/* const */ unsigned __sfrbit32 CWD            : 1;
		/* const */ unsigned __sfrbit32 PPC            : 1;
		/* const */ unsigned __sfrbit32 EPN            : 8;
		/* const */ unsigned __sfrbit32 EPC            : 16;
	} B;
	int I;
	unsigned int U;

} PCP_ES_type;
#define PCP_ES	(*(PCP_ES_type*) 0xf0043f14u)	/* PCP Error/Debug Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 P0T            : 2;
		/* const */ unsigned __sfrbit32 P1T            : 2;
		/* const */ unsigned __sfrbit32 P2T            : 2;
		/* const */ unsigned __sfrbit32 P3T            : 2;
		/* const */ unsigned __sfrbit32 IP0E           : 1;
		/* const */ unsigned __sfrbit32 IP1E           : 1;
		/* const */ unsigned __sfrbit32 IP2E           : 1;
		/* const */ unsigned __sfrbit32 IP3E           : 1;
		/* const */ unsigned __sfrbit32                : 20;
	} B;
	int I;
	unsigned int U;

} PCP_ICON_type;
#define PCP_ICON	(*(PCP_ICON_type*) 0xf0043f28u)	/* PCP Interrupt Configuration Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 CPPN           : 8;
		/* const */ unsigned __sfrbit32 IE             : 1;
		unsigned __sfrbit32                : 7;
		/* const */ unsigned __sfrbit32 PIPN           : 8;
		unsigned __sfrbit32 PARBCYC        : 2;
		unsigned __sfrbit32 PONECYC        : 1;
		unsigned __sfrbit32                : 5;
	} B;
	int I;
	unsigned int U;

} PCP_ICR_type;
#define PCP_ICR	(*(PCP_ICR_type*) 0xf0043f20u)	/* PCP Interrupt Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 REVNUM         : 8;
		/* const */ unsigned __sfrbit32 ID32BIT        : 8;
		/* const */ unsigned __sfrbit32 MODNUM         : 16;
	} B;
	int I;
	unsigned int U;

} PCP_ID_type;
#define PCP_ID	(*(PCP_ID_type*) 0xf0043f08u)	/* PCP Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 ITP            : 8;
		unsigned __sfrbit32                : 8;
		unsigned __sfrbit32 ITL            : 4;
		unsigned __sfrbit32                : 12;
	} B;
	int I;
	unsigned int U;

} PCP_ITR_type;
#define PCP_ITR	(*(PCP_ITR_type*) 0xf0043f24u)	/* PCP Interrupt Threshold Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 SRPN           : 8;
		/* const */ unsigned __sfrbit32                : 2;
		/* const */ unsigned __sfrbit32 TOS            : 2;
		/* const */ unsigned __sfrbit32 SRE            : 1;
		/* const */ unsigned __sfrbit32 SRR            : 1;
		/* const */ unsigned __sfrbit32                : 18;
	} B;
	int I;
	unsigned int U;

} PCP_SRC0_type;
#define PCP_SRC0	(*(PCP_SRC0_type*) 0xf0043ffcu)	/* PCP Service Request Control Register 0  */
#define PCP_SRC1	(*(PCP_SRC0_type*) 0xf0043ff8u)	/* PCP Service Request Control Register 1  */
#define PCP_SRC2	(*(PCP_SRC0_type*) 0xf0043ff4u)	/* PCP Service Request Control Register 2  */
#define PCP_SRC3	(*(PCP_SRC0_type*) 0xf0043ff0u)	/* PCP Service Request Control Register 3  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 SRPN           : 8;
		/* const */ unsigned __sfrbit32                : 2;
		/* const */ unsigned __sfrbit32 TOS            : 2;
		/* const */ unsigned __sfrbit32 SRE            : 1;
		/* const */ unsigned __sfrbit32 SRR            : 1;
		/* const */ unsigned __sfrbit32                : 2;
		/* const */ unsigned __sfrbit32 SRCN           : 8;
		/* const */ unsigned __sfrbit32                : 4;
		/* const */ unsigned __sfrbit32 RRQ            : 1;
		/* const */ unsigned __sfrbit32                : 3;
	} B;
	int I;
	unsigned int U;

} PCP_SRC10_type;
#define PCP_SRC10	(*(PCP_SRC10_type*) 0xf0043fd4u)	/* PCP Service Request Control Register 10  */
#define PCP_SRC11	(*(PCP_SRC10_type*) 0xf0043fd0u)	/* PCP Service Request Control Register 11  */
#define PCP_SRC9	(*(PCP_SRC10_type*) 0xf0043fd8u)	/* PCP Service Request Control Register 9  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 SRPN           : 8;
		unsigned __sfrbit32                : 2;
		unsigned __sfrbit32 TOS            : 2;
		/* const */ unsigned __sfrbit32 SRE            : 1;
		/* const */ unsigned __sfrbit32 SRR            : 1;
		unsigned __sfrbit32                : 18;
	} B;
	int I;
	unsigned int U;

} PCP_SRC4_type;
#define PCP_SRC4	(*(PCP_SRC4_type*) 0xf0043fecu)	/* PCP Service Request Control Register 4  */
#define PCP_SRC5	(*(PCP_SRC4_type*) 0xf0043fe8u)	/* PCP Service Request Control Register 5  */
#define PCP_SRC6	(*(PCP_SRC4_type*) 0xf0043fe4u)	/* PCP Service Request Control Register 6  */
#define PCP_SRC7	(*(PCP_SRC4_type*) 0xf0043fe0u)	/* PCP Service Request Control Register 7  */
#define PCP_SRC8	(*(PCP_SRC4_type*) 0xf0043fdcu)	/* PCP Service Request Control Register 8  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 SSRN           : 8;
		/* const */ unsigned __sfrbit32 STOS           : 2;
		/* const */ unsigned __sfrbit32                : 5;
		/* const */ unsigned __sfrbit32 ST             : 1;
		/* const */ unsigned __sfrbit32 SCHN           : 8;
		/* const */ unsigned __sfrbit32                : 8;
	} B;
	int I;
	unsigned int U;

} PCP_SSR_type;
#define PCP_SSR	(*(PCP_SSR_type*) 0xf0043f2cu)	/* PCP Stall Status Register  */


/* DMA */
typedef volatile union
{
	struct
	{ 
		unsigned int SMF            : 3;
		unsigned int INCS           : 1;
		unsigned int DMF            : 3;
		unsigned int INCD           : 1;
		unsigned int CBLS           : 4;
		unsigned int CBLD           : 4;
		unsigned int SHCT           : 2;
		unsigned int SHWEN          : 1;
		unsigned int                : 13;
	} B;
	int I;
	unsigned int U;

} DMA_ADRCR00_type;
#define DMA_ADRCR00	(*(DMA_ADRCR00_type*) 0xf0003c8cu)	/* DMA Channel 00 Address Control Register  */
#define DMA_ADRCR01	(*(DMA_ADRCR00_type*) 0xf0003cacu)	/* DMA Channel 01 Address Control Register  */
#define DMA_ADRCR02	(*(DMA_ADRCR00_type*) 0xf0003cccu)	/* DMA Channel 02 Address Control Register  */
#define DMA_ADRCR03	(*(DMA_ADRCR00_type*) 0xf0003cecu)	/* DMA Channel 03 Address Control Register  */
#define DMA_ADRCR04	(*(DMA_ADRCR00_type*) 0xf0003d0cu)	/* DMA Channel 04 Address Control Register  */
#define DMA_ADRCR05	(*(DMA_ADRCR00_type*) 0xf0003d2cu)	/* DMA Channel 05 Address Control Register  */
#define DMA_ADRCR06	(*(DMA_ADRCR00_type*) 0xf0003d4cu)	/* DMA Channel 06 Address Control Register  */
#define DMA_ADRCR07	(*(DMA_ADRCR00_type*) 0xf0003d6cu)	/* DMA Channel 07 Address Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int TREL           : 10;
		unsigned int                : 2;
		unsigned int PRSEL          : 4;
		unsigned int BLKM           : 3;
		unsigned int RROAT          : 1;
		unsigned int CHMODE         : 1;
		unsigned int CHDW           : 2;
		unsigned int                : 1;
		unsigned int PATSEL         : 2;
		unsigned int                : 2;
		unsigned int CHPRIO         : 1;
		unsigned int                : 1;
		unsigned int DMAPRIO        : 2;
	} B;
	int I;
	unsigned int U;

} DMA_CHCR00_type;
#define DMA_CHCR00	(*(DMA_CHCR00_type*) 0xf0003c84u)	/* DMA Channel 00 Control Register  */
#define DMA_CHCR01	(*(DMA_CHCR00_type*) 0xf0003ca4u)	/* DMA Channel 01 Control Register  */
#define DMA_CHCR02	(*(DMA_CHCR00_type*) 0xf0003cc4u)	/* DMA Channel 02 Control Register  */
#define DMA_CHCR03	(*(DMA_CHCR00_type*) 0xf0003ce4u)	/* DMA Channel 03 Control Register  */
#define DMA_CHCR04	(*(DMA_CHCR00_type*) 0xf0003d04u)	/* DMA Channel 04 Control Register  */
#define DMA_CHCR05	(*(DMA_CHCR00_type*) 0xf0003d24u)	/* DMA Channel 05 Control Register  */
#define DMA_CHCR06	(*(DMA_CHCR00_type*) 0xf0003d44u)	/* DMA Channel 06 Control Register  */
#define DMA_CHCR07	(*(DMA_CHCR00_type*) 0xf0003d64u)	/* DMA Channel 07 Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int WRPSE          : 1;
		unsigned int WRPDE          : 1;
		unsigned int INTCT          : 2;
		unsigned int WRPP           : 4;
		unsigned int INTP           : 4;
		unsigned int IRDV           : 4;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} DMA_CHICR00_type;
#define DMA_CHICR00	(*(DMA_CHICR00_type*) 0xf0003c88u)	/* DMA Channel 00 Interrupt Control Register  */
#define DMA_CHICR01	(*(DMA_CHICR00_type*) 0xf0003ca8u)	/* DMA Channel 01 Interrupt Control Register  */
#define DMA_CHICR02	(*(DMA_CHICR00_type*) 0xf0003cc8u)	/* DMA Channel 02 Interrupt Control Register  */
#define DMA_CHICR03	(*(DMA_CHICR00_type*) 0xf0003ce8u)	/* DMA Channel 03 Interrupt Control Register  */
#define DMA_CHICR04	(*(DMA_CHICR00_type*) 0xf0003d08u)	/* DMA Channel 04 Interrupt Control Register  */
#define DMA_CHICR05	(*(DMA_CHICR00_type*) 0xf0003d28u)	/* DMA Channel 05 Interrupt Control Register  */
#define DMA_CHICR06	(*(DMA_CHICR00_type*) 0xf0003d48u)	/* DMA Channel 06 Interrupt Control Register  */
#define DMA_CHICR07	(*(DMA_CHICR00_type*) 0xf0003d68u)	/* DMA Channel 07 Interrupt Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CH00           : 1;
		unsigned int CH01           : 1;
		unsigned int CH02           : 1;
		unsigned int CH03           : 1;
		unsigned int CH04           : 1;
		unsigned int CH05           : 1;
		unsigned int CH06           : 1;
		unsigned int CH07           : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} DMA_CHRSTR_type;
#define DMA_CHRSTR	(*(DMA_CHRSTR_type*) 0xf0003c10u)	/* DMA Channel Reset Request Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int TCOUNT         : 10;
		/* const */ unsigned int                : 5;
		/* const */ unsigned int LXO            : 1;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} DMA_CHSR00_type;
#define DMA_CHSR00	(*(DMA_CHSR00_type*) 0xf0003c80u)	/* DMA Channel 00 Status Register  */
#define DMA_CHSR01	(*(DMA_CHSR00_type*) 0xf0003ca0u)	/* DMA Channel 01 Status Register  */
#define DMA_CHSR02	(*(DMA_CHSR00_type*) 0xf0003cc0u)	/* DMA Channel 02 Status Register  */
#define DMA_CHSR03	(*(DMA_CHSR00_type*) 0xf0003ce0u)	/* DMA Channel 03 Status Register  */
#define DMA_CHSR04	(*(DMA_CHSR00_type*) 0xf0003d00u)	/* DMA Channel 04 Status Register  */
#define DMA_CHSR05	(*(DMA_CHSR00_type*) 0xf0003d20u)	/* DMA Channel 05 Status Register  */
#define DMA_CHSR06	(*(DMA_CHSR00_type*) 0xf0003d40u)	/* DMA Channel 06 Status Register  */
#define DMA_CHSR07	(*(DMA_CHSR00_type*) 0xf0003d60u)	/* DMA Channel 07 Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int ONE            : 1;
		unsigned int SBWE           : 1;
		unsigned int                : 27;
	} B;
	int I;
	unsigned int U;

} DMA_CLC_type;
#define DMA_CLC	(*(DMA_CLC_type*) 0xf0003c00u)	/* DMA Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CTL00          : 1;
		unsigned int CTL01          : 1;
		unsigned int CTL02          : 1;
		unsigned int CTL03          : 1;
		unsigned int CTL04          : 1;
		unsigned int CTL05          : 1;
		unsigned int CTL06          : 1;
		unsigned int CTL07          : 1;
		unsigned int                : 8;
		unsigned int CME0SER        : 1;
		unsigned int CME0DER        : 1;
		unsigned int                : 2;
		unsigned int CFPIER         : 1;
		unsigned int CLMBER         : 1;
		unsigned int CLCERBERUS     : 1;
		unsigned int                : 4;
		unsigned int CLRMLI0        : 1;
		unsigned int                : 4;
	} B;
	int I;
	unsigned int U;

} DMA_CLRE_type;
#define DMA_CLRE	(*(DMA_CLRE_type*) 0xf0003c28u)	/* DMA Clear Error Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DADR           : 32;
	} B;
	int I;
	unsigned int U;

} DMA_DADR00_type;
#define DMA_DADR00	(*(DMA_DADR00_type*) 0xf0003c94u)	/* DMA Channel 00 Destination Address Register  */
#define DMA_DADR01	(*(DMA_DADR00_type*) 0xf0003cb4u)	/* DMA Channel 01 Destination Address Register  */
#define DMA_DADR02	(*(DMA_DADR00_type*) 0xf0003cd4u)	/* DMA Channel 02 Destination Address Register  */
#define DMA_DADR03	(*(DMA_DADR00_type*) 0xf0003cf4u)	/* DMA Channel 03 Destination Address Register  */
#define DMA_DADR04	(*(DMA_DADR00_type*) 0xf0003d14u)	/* DMA Channel 04 Destination Address Register  */
#define DMA_DADR05	(*(DMA_DADR00_type*) 0xf0003d34u)	/* DMA Channel 05 Destination Address Register  */
#define DMA_DADR06	(*(DMA_DADR00_type*) 0xf0003d54u)	/* DMA Channel 06 Destination Address Register  */
#define DMA_DADR07	(*(DMA_DADR00_type*) 0xf0003d74u)	/* DMA Channel 07 Destination Address Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ETRL00         : 1;
		unsigned int ETRL01         : 1;
		unsigned int ETRL02         : 1;
		unsigned int ETRL03         : 1;
		unsigned int ETRL04         : 1;
		unsigned int ETRL05         : 1;
		unsigned int ETRL06         : 1;
		unsigned int ETRL07         : 1;
		unsigned int                : 8;
		unsigned int EME0SER        : 1;
		unsigned int EME0DER        : 1;
		unsigned int                : 2;
		unsigned int ME0INP         : 4;
		unsigned int                : 4;
		unsigned int TRLINP         : 4;
	} B;
	int I;
	unsigned int U;

} DMA_EER_type;
#define DMA_EER	(*(DMA_EER_type*) 0xf0003c20u)	/* DMA Enable Error Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int TRL00          : 1;
		/* const */ unsigned int TRL01          : 1;
		/* const */ unsigned int TRL02          : 1;
		/* const */ unsigned int TRL03          : 1;
		/* const */ unsigned int TRL04          : 1;
		/* const */ unsigned int TRL05          : 1;
		/* const */ unsigned int TRL06          : 1;
		/* const */ unsigned int TRL07          : 1;
		/* const */ unsigned int                : 8;
		/* const */ unsigned int ME0SER         : 1;
		/* const */ unsigned int ME0DER         : 1;
		/* const */ unsigned int                : 2;
		/* const */ unsigned int FPIER          : 1;
		/* const */ unsigned int LMBER          : 1;
		/* const */ unsigned int CERBERUSER     : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int LECME0         : 3;
		/* const */ unsigned int MLI0           : 1;
		/* const */ unsigned int                : 4;
	} B;
	int I;
	unsigned int U;

} DMA_ERRSR_type;
#define DMA_ERRSR	(*(DMA_ERRSR_type*) 0xf0003c24u)	/* DMA Error Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SIDMA0         : 1;
		unsigned int SIDMA1         : 1;
		unsigned int SIDMA2         : 1;
		unsigned int SIDMA3         : 1;
		unsigned int SIDMA4         : 1;
		unsigned int SIDMA5         : 1;
		unsigned int SIDMA6         : 1;
		unsigned int SIDMA7         : 1;
		unsigned int SIDMA8         : 1;
		unsigned int SIDMA9         : 1;
		unsigned int SIDMA10        : 1;
		unsigned int SIDMA11        : 1;
		unsigned int SIDMA12        : 1;
		unsigned int SIDMA13        : 1;
		unsigned int SIDMA14        : 1;
		unsigned int SIDMA15        : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} DMA_GINTR_type;
#define DMA_GINTR	(*(DMA_GINTR_type*) 0xf0003c2cu)	/* DMA Global Interrupt Set Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ECH00          : 1;
		unsigned int ECH01          : 1;
		unsigned int ECH02          : 1;
		unsigned int ECH03          : 1;
		unsigned int ECH04          : 1;
		unsigned int ECH05          : 1;
		unsigned int ECH06          : 1;
		unsigned int ECH07          : 1;
		unsigned int                : 8;
		unsigned int DCH00          : 1;
		unsigned int DCH01          : 1;
		unsigned int DCH02          : 1;
		unsigned int DCH03          : 1;
		unsigned int DCH04          : 1;
		unsigned int DCH05          : 1;
		unsigned int DCH06          : 1;
		unsigned int DCH07          : 1;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} DMA_HTREQ_type;
#define DMA_HTREQ	(*(DMA_HTREQ_type*) 0xf0003c1cu)	/* DMA Hardware Transaction Request Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MOD_REV        : 8;
		/* const */ unsigned int MOD_TYPE       : 8;
		/* const */ unsigned int MOD_NUMBER     : 16;
	} B;
	int I;
	unsigned int U;

} DMA_ID_type;
#define DMA_ID	(*(DMA_ID_type*) 0xf0003c08u)	/* Module Identification Register  */
#define MCHK_ID	(*(DMA_ID_type*) 0xf010c208u)	/* Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CICH00         : 1;
		unsigned int CICH01         : 1;
		unsigned int CICH02         : 1;
		unsigned int CICH03         : 1;
		unsigned int CICH04         : 1;
		unsigned int CICH05         : 1;
		unsigned int CICH06         : 1;
		unsigned int CICH07         : 1;
		unsigned int                : 8;
		unsigned int CWRP00         : 1;
		unsigned int CWRP01         : 1;
		unsigned int CWRP02         : 1;
		unsigned int CWRP03         : 1;
		unsigned int CWRP04         : 1;
		unsigned int CWRP05         : 1;
		unsigned int CWRP06         : 1;
		unsigned int CWRP07         : 1;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} DMA_INTCR_type;
#define DMA_INTCR	(*(DMA_INTCR_type*) 0xf0003c58u)	/* DMA Interrupt Clear Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int ICH00          : 1;
		/* const */ unsigned int ICH01          : 1;
		/* const */ unsigned int ICH02          : 1;
		/* const */ unsigned int ICH03          : 1;
		/* const */ unsigned int ICH04          : 1;
		/* const */ unsigned int ICH05          : 1;
		/* const */ unsigned int ICH06          : 1;
		/* const */ unsigned int ICH07          : 1;
		/* const */ unsigned int                : 8;
		/* const */ unsigned int IPM00          : 1;
		/* const */ unsigned int IPM01          : 1;
		/* const */ unsigned int IPM02          : 1;
		/* const */ unsigned int IPM03          : 1;
		/* const */ unsigned int IPM04          : 1;
		/* const */ unsigned int IPM05          : 1;
		/* const */ unsigned int IPM06          : 1;
		/* const */ unsigned int IPM07          : 1;
		/* const */ unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} DMA_INTSR_type;
#define DMA_INTSR	(*(DMA_INTSR_type*) 0xf0003c54u)	/* DMA Interrupt Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int AEN0           : 1;
		unsigned int AEN1           : 1;
		unsigned int AEN2           : 1;
		unsigned int AEN3           : 1;
		unsigned int AEN4           : 1;
		unsigned int AEN5           : 1;
		unsigned int AEN6           : 1;
		unsigned int AEN7           : 1;
		unsigned int AEN8           : 1;
		unsigned int AEN9           : 1;
		unsigned int AEN10          : 1;
		unsigned int AEN11          : 1;
		unsigned int AEN12          : 1;
		unsigned int AEN13          : 1;
		unsigned int AEN14          : 1;
		unsigned int AEN15          : 1;
		unsigned int AEN16          : 1;
		unsigned int AEN17          : 1;
		unsigned int AEN18          : 1;
		unsigned int AEN19          : 1;
		unsigned int AEN20          : 1;
		unsigned int AEN21          : 1;
		unsigned int AEN22          : 1;
		unsigned int AEN23          : 1;
		unsigned int AEN24          : 1;
		unsigned int AEN25          : 1;
		unsigned int AEN26          : 1;
		unsigned int AEN27          : 1;
		unsigned int AEN28          : 1;
		unsigned int AEN29          : 1;
		unsigned int AEN30          : 1;
		unsigned int AEN31          : 1;
	} B;
	int I;
	unsigned int U;

} DMA_ME0AENR_type;
#define DMA_ME0AENR	(*(DMA_ME0AENR_type*) 0xf0003c44u)	/* DMA Move Engine 0 Access Enable Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SLICE0         : 5;
		unsigned int SIZE0          : 3;
		unsigned int SLICE1         : 5;
		unsigned int SIZE1          : 3;
		unsigned int SLICE2         : 5;
		unsigned int SIZE2          : 3;
		unsigned int SLICE3         : 5;
		unsigned int SIZE3          : 3;
	} B;
	int I;
	unsigned int U;

} DMA_ME0ARR_type;
#define DMA_ME0ARR	(*(DMA_ME0ARR_type*) 0xf0003c48u)	/* DMA Move Engine 0 Access Range Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PAT00          : 8;
		unsigned int PAT01          : 8;
		unsigned int PAT02          : 8;
		unsigned int PAT03          : 8;
	} B;
	int I;
	unsigned int U;

} DMA_ME0PR_type;
#define DMA_ME0PR	(*(DMA_ME0PR_type*) 0xf0003c3cu)	/* DMA Move Engine 0 Pattern Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RD00           : 8;
		/* const */ unsigned int RD01           : 8;
		/* const */ unsigned int RD02           : 8;
		/* const */ unsigned int RD03           : 8;
	} B;
	int I;
	unsigned int U;

} DMA_ME0R_type;
#define DMA_ME0R	(*(DMA_ME0R_type*) 0xf0003c34u)	/* DMA Move Engine 0 Read Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int ME0RS          : 1;
		/* const */ unsigned int CH0            : 3;
		/* const */ unsigned int ME0WS          : 1;
		/* const */ unsigned int RBTFPI         : 3;
		/* const */ unsigned int                : 5;
		/* const */ unsigned int RBTLMB         : 3;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} DMA_MESR_type;
#define DMA_MESR	(*(DMA_MESR_type*) 0xf0003c30u)	/* DMA Move Engine Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} DMA_MLI0SRC0_type;
#define DMA_MLI0SRC0	(*(DMA_MLI0SRC0_type*) 0xf0003eacu)	/* DMA MLI0 Service Request Control Register 0  */
#define DMA_MLI0SRC1	(*(DMA_MLI0SRC0_type*) 0xf0003ea8u)	/* DMA MLI0 Service Request Control Register 1  */
#define DMA_MLI0SRC2	(*(DMA_MLI0SRC0_type*) 0xf0003ea4u)	/* DMA MLI0 Service Request Control Register 2  */
#define DMA_MLI0SRC3	(*(DMA_MLI0SRC0_type*) 0xf0003ea0u)	/* DMA MLI0 Service Request Control Register 3  */
#define DMA_SRC0	(*(DMA_MLI0SRC0_type*) 0xf0003efcu)	/* DMA Service Request Control Register 0  */
#define DMA_SRC1	(*(DMA_MLI0SRC0_type*) 0xf0003ef8u)	/* DMA Service Request Control Register 1  */
#define DMA_SRC2	(*(DMA_MLI0SRC0_type*) 0xf0003ef4u)	/* DMA Service Request Control Register 2  */
#define DMA_SRC3	(*(DMA_MLI0SRC0_type*) 0xf0003ef0u)	/* DMA Service Request Control Register 3  */
#define DMA_SRC4	(*(DMA_MLI0SRC0_type*) 0xf0003eecu)	/* DMA Service Request Control Register 4  */
#define DMA_SRC5	(*(DMA_MLI0SRC0_type*) 0xf0003ee8u)	/* DMA Service Request Control Register 5  */
#define DMA_SRC6	(*(DMA_MLI0SRC0_type*) 0xf0003ee4u)	/* DMA Service Request Control Register 6  */
#define DMA_SRC7	(*(DMA_MLI0SRC0_type*) 0xf0003ee0u)	/* DMA Service Request Control Register 7  */

typedef volatile union
{
	struct
	{ 
		unsigned int BTRC0          : 2;
		unsigned int BCHS0          : 3;
		unsigned int BRL0           : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} DMA_OCDSR_type;
#define DMA_OCDSR	(*(DMA_OCDSR_type*) 0xf0003c64u)	/* DMA OCDS Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SADR           : 32;
	} B;
	int I;
	unsigned int U;

} DMA_SADR00_type;
#define DMA_SADR00	(*(DMA_SADR00_type*) 0xf0003c90u)	/* DMA Channel 00 Source Address Register  */
#define DMA_SADR01	(*(DMA_SADR00_type*) 0xf0003cb0u)	/* DMA Channel 01 Source Address Register  */
#define DMA_SADR02	(*(DMA_SADR00_type*) 0xf0003cd0u)	/* DMA Channel 02 Source Address Register  */
#define DMA_SADR03	(*(DMA_SADR00_type*) 0xf0003cf0u)	/* DMA Channel 03 Source Address Register  */
#define DMA_SADR04	(*(DMA_SADR00_type*) 0xf0003d10u)	/* DMA Channel 04 Source Address Register  */
#define DMA_SADR05	(*(DMA_SADR00_type*) 0xf0003d30u)	/* DMA Channel 05 Source Address Register  */
#define DMA_SADR06	(*(DMA_SADR00_type*) 0xf0003d50u)	/* DMA Channel 06 Source Address Register  */
#define DMA_SADR07	(*(DMA_SADR00_type*) 0xf0003d70u)	/* DMA Channel 07 Source Address Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SHADR          : 32;
	} B;
	int I;
	unsigned int U;

} DMA_SHADR00_type;
#define DMA_SHADR00	(*(DMA_SHADR00_type*) 0xf0003c98u)	/* DMA Channel 00 Shadow Address Register  */
#define DMA_SHADR01	(*(DMA_SHADR00_type*) 0xf0003cb8u)	/* DMA Channel 01 Shadow Address Register  */
#define DMA_SHADR02	(*(DMA_SHADR00_type*) 0xf0003cd8u)	/* DMA Channel 02 Shadow Address Register  */
#define DMA_SHADR03	(*(DMA_SHADR00_type*) 0xf0003cf8u)	/* DMA Channel 03 Shadow Address Register  */
#define DMA_SHADR04	(*(DMA_SHADR00_type*) 0xf0003d18u)	/* DMA Channel 04 Shadow Address Register  */
#define DMA_SHADR05	(*(DMA_SHADR00_type*) 0xf0003d38u)	/* DMA Channel 05 Shadow Address Register  */
#define DMA_SHADR06	(*(DMA_SHADR00_type*) 0xf0003d58u)	/* DMA Channel 06 Shadow Address Register  */
#define DMA_SHADR07	(*(DMA_SHADR00_type*) 0xf0003d78u)	/* DMA Channel 07 Shadow Address Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SCH00          : 1;
		unsigned int SCH01          : 1;
		unsigned int SCH02          : 1;
		unsigned int SCH03          : 1;
		unsigned int SCH04          : 1;
		unsigned int SCH05          : 1;
		unsigned int SCH06          : 1;
		unsigned int SCH07          : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} DMA_STREQ_type;
#define DMA_STREQ	(*(DMA_STREQ_type*) 0xf0003c18u)	/* DMA Software Transaction Request Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SUSEN00        : 1;
		unsigned int SUSEN01        : 1;
		unsigned int SUSEN02        : 1;
		unsigned int SUSEN03        : 1;
		unsigned int SUSEN04        : 1;
		unsigned int SUSEN05        : 1;
		unsigned int SUSEN06        : 1;
		unsigned int SUSEN07        : 1;
		unsigned int                : 8;
		/* const */ unsigned int SUSAC00        : 1;
		/* const */ unsigned int SUSAC01        : 1;
		/* const */ unsigned int SUSAC02        : 1;
		/* const */ unsigned int SUSAC03        : 1;
		/* const */ unsigned int SUSAC04        : 1;
		/* const */ unsigned int SUSAC05        : 1;
		/* const */ unsigned int SUSAC06        : 1;
		/* const */ unsigned int SUSAC07        : 1;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} DMA_SUSPMR_type;
#define DMA_SUSPMR	(*(DMA_SUSPMR_type*) 0xf0003c68u)	/* DMA Suspend Mode Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int CH00           : 1;
		/* const */ unsigned int CH01           : 1;
		/* const */ unsigned int CH02           : 1;
		/* const */ unsigned int CH03           : 1;
		/* const */ unsigned int CH04           : 1;
		/* const */ unsigned int CH05           : 1;
		/* const */ unsigned int CH06           : 1;
		/* const */ unsigned int CH07           : 1;
		/* const */ unsigned int                : 8;
		/* const */ unsigned int HTRE00         : 1;
		/* const */ unsigned int HTRE01         : 1;
		/* const */ unsigned int HTRE02         : 1;
		/* const */ unsigned int HTRE03         : 1;
		/* const */ unsigned int HTRE04         : 1;
		/* const */ unsigned int HTRE05         : 1;
		/* const */ unsigned int HTRE06         : 1;
		/* const */ unsigned int HTRE07         : 1;
		/* const */ unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} DMA_TRSR_type;
#define DMA_TRSR	(*(DMA_TRSR_type*) 0xf0003c14u)	/* DMA Transaction Request State Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int WRPS00         : 1;
		/* const */ unsigned int WRPS01         : 1;
		/* const */ unsigned int WRPS02         : 1;
		/* const */ unsigned int WRPS03         : 1;
		/* const */ unsigned int WRPS04         : 1;
		/* const */ unsigned int WRPS05         : 1;
		/* const */ unsigned int WRPS06         : 1;
		/* const */ unsigned int WRPS07         : 1;
		/* const */ unsigned int                : 8;
		/* const */ unsigned int WRPD00         : 1;
		/* const */ unsigned int WRPD01         : 1;
		/* const */ unsigned int WRPD02         : 1;
		/* const */ unsigned int WRPD03         : 1;
		/* const */ unsigned int WRPD04         : 1;
		/* const */ unsigned int WRPD05         : 1;
		/* const */ unsigned int WRPD06         : 1;
		/* const */ unsigned int WRPD07         : 1;
		/* const */ unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} DMA_WRPSR_type;
#define DMA_WRPSR	(*(DMA_WRPSR_type*) 0xf0003c5cu)	/* DMA Wrap Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MCHKIN         : 32;
	} B;
	int I;
	unsigned int U;

} MCHK_IR_type;
#define MCHK_IR	(*(MCHK_IR_type*) 0xf010c210u)	/* Memory Checker Input Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MCHKR          : 32;
	} B;
	int I;
	unsigned int U;

} MCHK_RR_type;
#define MCHK_RR	(*(MCHK_RR_type*) 0xf010c214u)	/* Memory Checker Result Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int WO             : 32;
	} B;
	int I;
	unsigned int U;

} MCHK_WR_type;
#define MCHK_WR	(*(MCHK_WR_type*) 0xf010c220u)	/* Memory Checker Write Register  */


/* STM */
typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int STM_55_32_     : 24;
		/* const */ unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} STM_CAP_type;
#define STM_CAP	(*(STM_CAP_type*) 0xf000022cu)	/* STM Timer Capture Register  */
#define STM_TIM6	(*(STM_CAP_type*) 0xf0000228u)	/* STM Timer Register 6  */

typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 2;
		unsigned int RMC            : 3;
		unsigned int                : 21;
	} B;
	int I;
	unsigned int U;

} STM_CLC_type;
#define STM_CLC	(*(STM_CLC_type*) 0xf0000200u)	/* STM Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MSIZE0         : 5;
		unsigned int                : 3;
		unsigned int MSTART0        : 5;
		unsigned int                : 3;
		unsigned int MSIZE1         : 5;
		unsigned int                : 3;
		unsigned int MSTART1        : 5;
		unsigned int                : 3;
	} B;
	int I;
	unsigned int U;

} STM_CMCON_type;
#define STM_CMCON	(*(STM_CMCON_type*) 0xf0000238u)	/* STM Compare Match Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CMPVAL         : 32;
	} B;
	int I;
	unsigned int U;

} STM_CMP0_type;
#define STM_CMP0	(*(STM_CMP0_type*) 0xf0000230u)	/* STM Compare Register 0  */
#define STM_CMP1	(*(STM_CMP0_type*) 0xf0000234u)	/* STM Compare Register 1  */

typedef volatile union
{
	struct
	{ 
		unsigned int CMP0EN         : 1;
		/* const */ unsigned int CMP0IR         : 1;
		unsigned int CMP0OS         : 1;
		unsigned int                : 1;
		unsigned int CMP1EN         : 1;
		/* const */ unsigned int CMP1IR         : 1;
		unsigned int CMP1OS         : 1;
		unsigned int                : 25;
	} B;
	int I;
	unsigned int U;

} STM_ICR_type;
#define STM_ICR	(*(STM_ICR_type*) 0xf000023cu)	/* STM Interrupt Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MODREV         : 8;
		/* const */ unsigned int MODTYPE        : 8;
		/* const */ unsigned int MODNUM         : 16;
	} B;
	int I;
	unsigned int U;

} STM_ID_type;
#define STM_ID	(*(STM_ID_type*) 0xf0000208u)	/* STM Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CMP0IRR        : 1;
		unsigned int CMP0IRS        : 1;
		unsigned int CMP1IRR        : 1;
		unsigned int CMP1IRS        : 1;
		unsigned int                : 28;
	} B;
	int I;
	unsigned int U;

} STM_ISRR_type;
#define STM_ISRR	(*(STM_ISRR_type*) 0xf0000240u)	/* STM Interrupt Set/Reset Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} STM_SRC0_type;
#define STM_SRC0	(*(STM_SRC0_type*) 0xf00002fcu)	/* STM Service Request Control Register 0  */
#define STM_SRC1	(*(STM_SRC0_type*) 0xf00002f8u)	/* STM Service Request Control Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int STM_31_0_      : 32;
	} B;
	int I;
	unsigned int U;

} STM_TIM0_type;
#define STM_TIM0	(*(STM_TIM0_type*) 0xf0000210u)	/* STM Timer Register 0  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int STM_35_4_      : 32;
	} B;
	int I;
	unsigned int U;

} STM_TIM1_type;
#define STM_TIM1	(*(STM_TIM1_type*) 0xf0000214u)	/* STM Timer Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int STM_39_8_      : 32;
	} B;
	int I;
	unsigned int U;

} STM_TIM2_type;
#define STM_TIM2	(*(STM_TIM2_type*) 0xf0000218u)	/* STM Timer Register 2  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int STM_43_12_     : 32;
	} B;
	int I;
	unsigned int U;

} STM_TIM3_type;
#define STM_TIM3	(*(STM_TIM3_type*) 0xf000021cu)	/* STM Timer Register 3  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int STM_47_16_     : 32;
	} B;
	int I;
	unsigned int U;

} STM_TIM4_type;
#define STM_TIM4	(*(STM_TIM4_type*) 0xf0000220u)	/* STM Timer Register 4  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int STM_51_20_     : 32;
	} B;
	int I;
	unsigned int U;

} STM_TIM5_type;
#define STM_TIM5	(*(STM_TIM5_type*) 0xf0000224u)	/* STM Timer Register 5  */


/* Cerberus */
typedef volatile union
{
	struct
	{ 
		unsigned int DATA           : 32;
	} B;
	int I;
	unsigned int U;

} CBS_COMDATA_type;
#define CBS_COMDATA	(*(CBS_COMDATA_type*) 0xf0000468u)	/* Communication Mode Data Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ADDR           : 32;
	} B;
	int I;
	unsigned int U;

} CBS_ICTSA_type;
#define CBS_ICTSA	(*(CBS_ICTSA_type*) 0xf0000488u)	/* Internally Controlled Trace Source Register  */
#define CBS_ICTTA	(*(CBS_ICTSA_type*) 0xf000048cu)	/* Internally Controlled Trace Destination Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SET_CRS        : 1;
		unsigned int SET_CWS        : 1;
		unsigned int SET_CS         : 1;
		unsigned int CLR_CS         : 1;
		unsigned int CHANNEL_P      : 1;
		unsigned int CHANNEL        : 3;
		unsigned int                : 8;
		unsigned int SET_INT_MOD    : 1;
		unsigned int                : 1;
		unsigned int SET_INT_TRC    : 1;
		unsigned int CLR_INT_TRC    : 1;
		unsigned int TRC_MOD_P      : 1;
		unsigned int TRC_MOD        : 2;
		unsigned int                : 1;
		/* const */ unsigned int INT_MOD        : 1;
		/* const */ unsigned int INT_TRC        : 1;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} CBS_INTMOD_type;
#define CBS_INTMOD	(*(CBS_INTMOD_type*) 0xf0000484u)	/* Internal Mode Status and Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		/* const */ unsigned int CRSYNC         : 1;
		/* const */ unsigned int CWSYNC         : 1;
		unsigned int CW_ACK         : 1;
		/* const */ unsigned int COM_SYNC       : 1;
		/* const */ unsigned int HOSTED         : 1;
		unsigned int                : 3;
		/* const */ unsigned int CHANNEL        : 3;
		unsigned int                : 17;
	} B;
	int I;
	unsigned int U;

} CBS_IOSR_type;
#define CBS_IOSR	(*(CBS_IOSR_type*) 0xf000046cu)	/* IOClient Status and Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int JTAG_ID        : 32;
	} B;
	int I;
	unsigned int U;

} CBS_JTAGID_type;
#define CBS_JTAGID	(*(CBS_JTAGID_type*) 0xf0000464u)	/* JTAG Device Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int BSSB           : 1;
		unsigned int BSDMA          : 1;
		unsigned int BSML0          : 1;
		unsigned int BSML1          : 1;
		unsigned int BSPCP          : 1;
		unsigned int BSTC           : 1;
		unsigned int BSPCPEN        : 1;
		unsigned int BSHLTEN        : 1;
		unsigned int BTMCD          : 1;
		unsigned int                : 3;
		unsigned int BTPCP          : 1;
		unsigned int BTTC           : 1;
		unsigned int BTPCPEN        : 1;
		unsigned int                : 1;
		unsigned int BSP0           : 1;
		unsigned int BSP1           : 1;
		unsigned int BTP0           : 1;
		unsigned int BTP1           : 1;
		unsigned int BTT            : 1;
		unsigned int BTPS           : 2;
		unsigned int BTSS           : 1;
		unsigned int BTTIEN         : 1;
		unsigned int                : 7;
	} B;
	int I;
	unsigned int U;

} CBS_MCDBBS_type;
#define CBS_MCDBBS	(*(CBS_MCDBBS_type*) 0xf0000470u)	/* Break Bus Switch Configuration Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int BSSSB          : 1;
		/* const */ unsigned int BSSDMA         : 1;
		/* const */ unsigned int BSSML0         : 1;
		/* const */ unsigned int BSSML1         : 1;
		/* const */ unsigned int BSSPCP         : 1;
		/* const */ unsigned int BSSTC          : 1;
		unsigned int                : 2;
		/* const */ unsigned int BSCSB          : 1;
		/* const */ unsigned int BSCDMA         : 1;
		/* const */ unsigned int BSCML0         : 1;
		/* const */ unsigned int BSCML1         : 1;
		/* const */ unsigned int BSCPCP         : 1;
		/* const */ unsigned int BSCTC          : 1;
		unsigned int                : 2;
		/* const */ unsigned int BBS0           : 1;
		/* const */ unsigned int BBS1           : 1;
		/* const */ unsigned int BBC0           : 1;
		/* const */ unsigned int BBC1           : 1;
		unsigned int                : 4;
		unsigned int CAPCLR         : 1;
		unsigned int                : 7;
	} B;
	int I;
	unsigned int U;

} CBS_MCDBBSS_type;
#define CBS_MCDBBSS	(*(CBS_MCDBBSS_type*) 0xf0000490u)	/* Break Bus Switch Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int BTSCL          : 1;
		unsigned int                : 5;
		unsigned int SUS_P          : 1;
		unsigned int SUS            : 1;
		unsigned int BTS_P          : 1;
		unsigned int BTSEN          : 1;
		unsigned int BTSM           : 1;
		unsigned int                : 5;
		/* const */ unsigned int SSSTC          : 1;
		unsigned int                : 1;
		/* const */ unsigned int SSSSCU         : 1;
		/* const */ unsigned int SSSMCD         : 1;
		unsigned int                : 2;
		/* const */ unsigned int SSSBRK         : 1;
		unsigned int                : 1;
		/* const */ unsigned int SOS            : 1;
		/* const */ unsigned int SDS            : 1;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} CBS_MCDSSG_type;
#define CBS_MCDSSG	(*(CBS_MCDSSG_type*) 0xf0000474u)	/* Suspend Source Status and Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STC_P          : 1;
		unsigned int STCM           : 1;
		unsigned int STCTC          : 1;
		unsigned int STCPCP         : 1;
		unsigned int STCDMA         : 1;
		unsigned int                : 27;
	} B;
	int I;
	unsigned int U;

} CBS_MCDSSGC_type;
#define CBS_MCDSSGC	(*(CBS_MCDSSGC_type*) 0xf0000494u)	/* Suspend Signal Target Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int OC0_P          : 1;
		unsigned int OC0            : 1;
		unsigned int OC1_P          : 1;
		unsigned int OC1            : 1;
		unsigned int OC2_P          : 1;
		unsigned int OC2            : 1;
		unsigned int OC3_P          : 1;
		unsigned int OC3            : 1;
		unsigned int OC4_P          : 1;
		unsigned int OC4            : 1;
		unsigned int OC5_P          : 1;
		unsigned int OC5            : 1;
		unsigned int WDTSUS_P       : 1;
		unsigned int WDTSUS         : 1;
		unsigned int STABLE_P       : 1;
		unsigned int STABLE         : 1;
		unsigned int OJC0_P         : 1;
		unsigned int OJC0           : 1;
		unsigned int OJC1_P         : 1;
		unsigned int OJC1           : 1;
		unsigned int OJC2_P         : 1;
		unsigned int OJC2           : 1;
		unsigned int OJC3_P         : 1;
		unsigned int OJC3           : 1;
		unsigned int OJC4_P         : 1;
		unsigned int OJC4           : 1;
		unsigned int OJC5_P         : 1;
		unsigned int OJC5           : 1;
		unsigned int OJC6_P         : 1;
		unsigned int OJC6           : 1;
		unsigned int OJC7_P         : 1;
		unsigned int OJC7           : 1;
	} B;
	int I;
	unsigned int U;

} CBS_OCNTRL_type;
#define CBS_OCNTRL	(*(CBS_OCNTRL_type*) 0xf000047cu)	/* OSCU Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PAT            : 8;
		unsigned int DS             : 1;
		unsigned int                : 7;
		unsigned int IF_LCK_P       : 1;
		unsigned int IF_LCK         : 1;
		unsigned int AUT_OK_P       : 1;
		unsigned int AUT_OK         : 1;
		unsigned int                : 12;
	} B;
	int I;
	unsigned int U;

} CBS_OEC_type;
#define CBS_OEC	(*(CBS_OEC_type*) 0xf0000478u)	/* OCDS Enable Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int OEN            : 1;
		/* const */ unsigned int DJMODE         : 2;
		/* const */ unsigned int DAPRST         : 1;
		/* const */ unsigned int ENIDIS         : 1;
		/* const */ unsigned int EECTRC         : 1;
		/* const */ unsigned int EECDIS         : 1;
		/* const */ unsigned int WDTSUS         : 1;
		/* const */ unsigned int HARR           : 1;
		/* const */ unsigned int OJC1           : 1;
		/* const */ unsigned int OJC2           : 1;
		/* const */ unsigned int OJC3           : 1;
		/* const */ unsigned int RSTCL0         : 1;
		/* const */ unsigned int RSTCL1         : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int RSTCL3         : 1;
		/* const */ unsigned int IF_LCK         : 1;
		/* const */ unsigned int AUT_OK         : 1;
		/* const */ unsigned int STABLE         : 1;
		/* const */ unsigned int                : 13;
	} B;
	int I;
	unsigned int U;

} CBS_OSTATE_type;
#define CBS_OSTATE	(*(CBS_OSTATE_type*) 0xf0000480u)	/* OSCU Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 2;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} CBS_SRC0_type;
#define CBS_SRC0	(*(CBS_SRC0_type*) 0xf00004fcu)	/* Service Request Node1 Control Register  */
#define CBS_SRC1	(*(CBS_SRC0_type*) 0xf00004f8u)	/* Service Request Node2 Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int TRG0           : 1;
		/* const */ unsigned int TRG1           : 1;
		/* const */ unsigned int TRG2           : 1;
		/* const */ unsigned int TRG3           : 1;
		/* const */ unsigned int TRG4           : 1;
		/* const */ unsigned int TRG5           : 1;
		/* const */ unsigned int TRG6           : 1;
		/* const */ unsigned int TRG7           : 1;
		/* const */ unsigned int TRG8           : 1;
		/* const */ unsigned int TRG9           : 1;
		/* const */ unsigned int TRG10          : 1;
		/* const */ unsigned int TRG11          : 1;
		/* const */ unsigned int TRG12          : 1;
		/* const */ unsigned int TRG13          : 1;
		/* const */ unsigned int TRG14          : 1;
		/* const */ unsigned int TRG15          : 1;
		/* const */ unsigned int TRG16          : 1;
		/* const */ unsigned int TRG17          : 1;
		/* const */ unsigned int TRG18          : 1;
		/* const */ unsigned int TRG19          : 1;
		/* const */ unsigned int TRG20          : 1;
		/* const */ unsigned int TRG21          : 1;
		/* const */ unsigned int TRG22          : 1;
		/* const */ unsigned int TRG23          : 1;
		/* const */ unsigned int TRG24          : 1;
		/* const */ unsigned int TRG25          : 1;
		/* const */ unsigned int TRG26          : 1;
		/* const */ unsigned int TRG27          : 1;
		/* const */ unsigned int TRG28          : 1;
		/* const */ unsigned int TRG29          : 1;
		/* const */ unsigned int TRG30          : 1;
		/* const */ unsigned int TRG31          : 1;
	} B;
	int I;
	unsigned int U;

} CBS_TRIG_type;
#define CBS_TRIG	(*(CBS_TRIG_type*) 0xf00004a8u)	/* Trigger to Host Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int TRG0           : 1;
		unsigned int TRG1           : 1;
		unsigned int TRG2           : 1;
		unsigned int TRG3           : 1;
		unsigned int TRG4           : 1;
		unsigned int TRG5           : 1;
		unsigned int TRG6           : 1;
		unsigned int TRG7           : 1;
		unsigned int TRG8           : 1;
		unsigned int TRG9           : 1;
		unsigned int TRG10          : 1;
		unsigned int TRG11          : 1;
		unsigned int TRG12          : 1;
		unsigned int TRG13          : 1;
		unsigned int TRG14          : 1;
		unsigned int TRG15          : 1;
		unsigned int TRG16          : 1;
		unsigned int TRG17          : 1;
		unsigned int TRG18          : 1;
		unsigned int TRG19          : 1;
		unsigned int TRG20          : 1;
		unsigned int TRG21          : 1;
		unsigned int TRG22          : 1;
		unsigned int TRG23          : 1;
		unsigned int TRG24          : 1;
		unsigned int TRG25          : 1;
		unsigned int TRG26          : 1;
		unsigned int TRG27          : 1;
		unsigned int TRG28          : 1;
		unsigned int TRG29          : 1;
		unsigned int TRG30          : 1;
		unsigned int TRG31          : 1;
	} B;
	int I;
	unsigned int U;

} CBS_TRIGC_type;
#define CBS_TRIGC	(*(CBS_TRIGC_type*) 0xf00004a4u)	/* Clear Trigger to Host Register  */
#define CBS_TRIGS	(*(CBS_TRIGC_type*) 0xf00004a0u)	/* Set Trigger to Host Register  */


/* ASC */
typedef volatile union
{
	struct
	{ 
		unsigned int BR_VALUE       : 13;
		unsigned int                : 19;
	} B;
	int I;
	unsigned int U;

} ASC0_BG_type;
#define ASC0_BG	(*(ASC0_BG_type*) 0xf0000a14u)	/* Baud Rate Timer/Reload Register  */
#define ASC1_BG	(*(ASC0_BG_type*) 0xf0000b14u)	/* Baud Rate Timer/Reload Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 2;
		unsigned int RMC            : 8;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ASC0_CLC_type;
#define ASC0_CLC	(*(ASC0_CLC_type*) 0xf0000a00u)	/* ASC0 Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int M              : 3;
		unsigned int STP            : 1;
		unsigned int REN            : 1;
		unsigned int PEN            : 1;
		unsigned int FEN            : 1;
		unsigned int OEN            : 1;
		unsigned int PE             : 1;
		unsigned int FE             : 1;
		unsigned int OE             : 1;
		unsigned int FDE            : 1;
		unsigned int ODD            : 1;
		unsigned int BRS            : 1;
		unsigned int LB             : 1;
		unsigned int R              : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ASC0_CON_type;
#define ASC0_CON	(*(ASC0_CON_type*) 0xf0000a10u)	/* Control Register  */
#define ASC1_CON	(*(ASC0_CON_type*) 0xf0000b10u)	/* Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ASC0_ESRC_type;
#define ASC0_ESRC	(*(ASC0_ESRC_type*) 0xf0000af8u)	/* Error Interrupt Service Request Control Register  */
#define ASC0_RSRC	(*(ASC0_ESRC_type*) 0xf0000af4u)	/* Receive Interrupt Service Request Control Register  */
#define ASC0_TBSRC	(*(ASC0_ESRC_type*) 0xf0000afcu)	/* Transmit Buffer Interrupt Service Request Control Register  */
#define ASC0_TSRC	(*(ASC0_ESRC_type*) 0xf0000af0u)	/* Transmit Interrupt Service Request Control Register  */
#define ASC1_ESRC	(*(ASC0_ESRC_type*) 0xf0000bf8u)	/* Error Interrupt Service Request Control Register  */
#define ASC1_RSRC	(*(ASC0_ESRC_type*) 0xf0000bf4u)	/* Receive Interrupt Service Request Control Register  */
#define ASC1_TBSRC	(*(ASC0_ESRC_type*) 0xf0000bfcu)	/* Transmit Buffer Interrupt Service Request Control Register  */
#define ASC1_TSRC	(*(ASC0_ESRC_type*) 0xf0000bf0u)	/* Transmit Interrupt Service Request Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int FD_VALUE       : 9;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} ASC0_FDV_type;
#define ASC0_FDV	(*(ASC0_FDV_type*) 0xf0000a18u)	/* Fractional Divider Register  */
#define ASC1_FDV	(*(ASC0_FDV_type*) 0xf0000b18u)	/* Fractional Divider Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MODREV         : 8;
		/* const */ unsigned int MODNUM         : 8;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ASC0_ID_type;
#define ASC0_ID	(*(ASC0_ID_type*) 0xf0000a08u)	/* Module Identification Register  */
#define ASC1_ID	(*(ASC0_ID_type*) 0xf0000b08u)	/* Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int RIS            : 1;
		unsigned int                : 31;
	} B;
	int I;
	unsigned int U;

} ASC0_PISEL_type;
#define ASC0_PISEL	(*(ASC0_PISEL_type*) 0xf0000a04u)	/* ASC0 Peripheral Input Select Register  */
#define ASC1_PISEL	(*(ASC0_PISEL_type*) 0xf0000b04u)	/* ASC1 Peripheral Input Select Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RD_VALUE       : 9;
		/* const */ unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} ASC0_RBUF_type;
#define ASC0_RBUF	(*(ASC0_RBUF_type*) 0xf0000a24u)	/* Receive Buffer Register  */
#define ASC1_RBUF	(*(ASC0_RBUF_type*) 0xf0000b24u)	/* Receive Buffer Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int TD_VALUE       : 9;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} ASC0_TBUF_type;
#define ASC0_TBUF	(*(ASC0_TBUF_type*) 0xf0000a20u)	/* Transmit Buffer Register  */
#define ASC1_TBUF	(*(ASC0_TBUF_type*) 0xf0000b20u)	/* Transmit Buffer Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int CLRREN         : 1;
		unsigned int SETREN         : 1;
		unsigned int                : 2;
		unsigned int CLRPE          : 1;
		unsigned int CLRFE          : 1;
		unsigned int CLROE          : 1;
		unsigned int SETPE          : 1;
		unsigned int SETFE          : 1;
		unsigned int SETOE          : 1;
		unsigned int                : 18;
	} B;
	int I;
	unsigned int U;

} ASC0_WHBCON_type;
#define ASC0_WHBCON	(*(ASC0_WHBCON_type*) 0xf0000a50u)	/* Write Hardware Bits Control Register  */
#define ASC1_WHBCON	(*(ASC0_WHBCON_type*) 0xf0000b50u)	/* Write Hardware Bits Control Register  */


/* SSC */
typedef volatile union
{
	struct
	{ 
		unsigned int BR_VALUE       : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_BR_type;
#define SSC0_BR	(*(SSC0_BR_type*) 0xf0100114u)	/* Baud Rate Timer Reload Register  */
#define SSC1_BR	(*(SSC0_BR_type*) 0xf0100214u)	/* Baud Rate Timer Reload Register  */
#define SSC2_BR	(*( SSC0_BR_type *) 0xf0100314u)	/* Baud Rate Timer Reload Register */

typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} SSC0_CLC_type;
#define SSC0_CLC	(*(SSC0_CLC_type*) 0xf0100100u)	/* SSC0_Clock Control Register  */
#define SSC1_CLC	(*(SSC0_CLC_type*) 0xf0100200u)	/* SSC1 Clock Control Register  */
#define SSC2_CLC	(*(SSC0_CLC_type*) 0xf0100300u)	/* SSC2 Clock Control Register */
typedef volatile union
{
	struct
	{ 
		unsigned int BM             : 4;
		unsigned int HB             : 1;
		unsigned int PH             : 1;
		unsigned int PO             : 1;
		unsigned int LB             : 1;
		unsigned int TEN            : 1;
		unsigned int REN            : 1;
		unsigned int PEN            : 1;
		unsigned int BEN            : 1;
		unsigned int AREN           : 1;
		unsigned int                : 1;
		unsigned int MS             : 1;
		unsigned int EN             : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_CON_type;
#define SSC0_CON	(*(SSC0_CON_type*) 0xf0100110u)	/* Control Register  */
#define SSC1_CON	(*(SSC0_CON_type*) 0xf0100210u)	/* Control Register  */
#define SSC2_CON	(*( SSC0_CON_type *) 0xf0100310u)	/* Control Register */
typedef volatile union
{
	struct
	{ 
		unsigned int                : 8;
		unsigned int CLRTE          : 1;
		unsigned int CLRRE          : 1;
		unsigned int CLRPE          : 1;
		unsigned int CLRBE          : 1;
		unsigned int SETTE          : 1;
		unsigned int SETRE          : 1;
		unsigned int SETPE          : 1;
		unsigned int SETBE          : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_EFM_type;
#define SSC0_EFM	(*(SSC0_EFM_type*) 0xf010012cu)	/* Error Flag Modification Register  */
#define SSC1_EFM	(*(SSC0_EFM_type*) 0xf010022cu)	/* Error Flag Modification Register  */
#define SSC2_EFM	(*( SSC0_EFM_type *) 0xf010032cu)	/* Error Flag Modification Register */
typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_ESRC_type;
#define SSC0_ESRC	(*( SSC0_ESRC_type *) 0xf01001fcu)	/* Error Interrupt Service Request Control Register */
#define SSC0_RSRC	(*( SSC0_ESRC_type *) 0xf01001f8u)	/* Receive Interrupt Service Request Control Register */
#define SSC0_TSRC	(*( SSC0_ESRC_type *) 0xf01001f4u)	/* Transmit Interrupt Service Request Control Register */
#define SSC1_ESRC	(*( SSC0_ESRC_type *) 0xf01002fcu)	/* Error Interrupt Service Request Control Register */
#define SSC1_RSRC	(*( SSC0_ESRC_type *) 0xf01002f8u)	/* Receive Interrupt Service Request Control Register */
#define SSC1_TSRC	(*( SSC0_ESRC_type *) 0xf01002f4u)	/* Transmit Interrupt Service Request Control Register */
#define SSC2_ESRC	(*( SSC0_ESRC_type *) 0xf01003fcu)	/* Error Interrupt Service Request Control Register */
#define SSC2_RSRC	(*( SSC0_ESRC_type *) 0xf01003f8u)	/* Receive Interrupt Service Request Control Register */
#define SSC2_TSRC	(*( SSC0_ESRC_type *) 0xf01003f4u)	/* Transmit Interrupt Service Request Control Register */

typedef volatile union
{
	struct
	{ 
		unsigned int STEP           : 10;
		unsigned int                : 1;
		unsigned int SM             : 1;
		unsigned int SC             : 2;
		unsigned int DM             : 2;
		/* const */ unsigned int RESULT         : 10;
		unsigned int                : 2;
		/* const */ unsigned int SUSACK         : 1;
		/* const */ unsigned int SUSREQ         : 1;
		unsigned int ENHW           : 1;
		unsigned int DISCLK         : 1;
	} B;
	int I;
	unsigned int U;

} SSC0_FDR_type;
#define SSC0_FDR	(*( SSC0_FDR_type *) 0xf010010cu)	/* SSC0 Fractional Divider Register */
#define SSC1_FDR	(*( SSC0_FDR_type *) 0xf010020cu)	/* SSC1 Fractional Divider Register */
#define SSC2_FDR	(*( SSC0_FDR_type *) 0xf010030cu)	/* SSC2 Fractional Divider Register */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MODREV         : 8;
		/* const */ unsigned int MODNUM         : 8;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_ID_type;
#define SSC0_ID	(*(SSC0_ID_type*) 0xf0100108u)	/* Module Identification Register  */
#define SSC1_ID	(*(SSC0_ID_type*) 0xf0100208u)	/* Module Identification Register  */
#define SSC2_ID	(*(SSC0_ID_type*) 0xf0100308u)	/* Module Identification Register  */
typedef volatile union
{
	struct
	{ 
		unsigned int MRIS           : 1;
		unsigned int SRIS           : 1;
		unsigned int SCIS           : 1;
		unsigned int SLSIS          : 3;
		unsigned int                : 2;
		unsigned int STIP           : 1;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} SSC0_PISEL_type;
#define SSC0_PISEL	(*(SSC0_PISEL_type*) 0xf0100104u)	/* Port Input Select Register  */
#define SSC1_PISEL	(*(SSC0_PISEL_type*) 0xf0100204u)	/* Port Input Select Register  */
#define SSC2_PISEL	(*(SSC0_PISEL_type*) 0xf0100304u)	/* Port Input Select Register  */
typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RB_VALUE       : 16;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_RB_type;

#define SSC0_RB	(*(SSC0_RB_type*) 0xf0100124u)	/* Receive Buffer Register  */
#define SSC1_RB	(*(SSC0_RB_type*) 0xf0100224u)	/* Receive Buffer Register  */
#define SSC2_RB	(*(SSC0_RB_type*) 0xf0100324u)	/* Receive Buffer Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int AOL0           : 1;
		unsigned int AOL1           : 1;
		unsigned int AOL2           : 1;
		unsigned int AOL3           : 1;
		unsigned int AOL4           : 1;
		unsigned int AOL5           : 1;
		unsigned int AOL6           : 1;
		unsigned int AOL7           : 1;
		unsigned int OEN0           : 1;
		unsigned int OEN1           : 1;
		unsigned int OEN2           : 1;
		unsigned int OEN3           : 1;
		unsigned int OEN4           : 1;
		unsigned int OEN5           : 1;
		unsigned int OEN6           : 1;
		unsigned int OEN7           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_SSOC_type;
#define SSC0_SSOC	(*( SSC0_SSOC_type *) 0xf0100118u)	/* Slave Select Output Control Register */
#define SSC1_SSOC	(*( SSC0_SSOC_type *) 0xf0100218u)	/* Slave Select Output Control Register */
#define SSC2_SSOC	(*( SSC0_SSOC_type *) 0xf0100318u)	/* Slave Select Output Control Register */

typedef volatile union
{
	struct
	{ 
		unsigned int LEAD           : 2;
		unsigned int TRAIL          : 2;
		unsigned int INACT          : 2;
		unsigned int                : 2;
		unsigned int SLSO7MOD       : 1;
		unsigned int                : 5;
		unsigned int QSMEN          : 1;
		unsigned int EN             : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_SSOTC_type;
#define SSC0_SSOTC	(*( SSC0_SSOTC_type *) 0xf010011cu)	/* Slave Select Output Timing Control Register */
#define SSC1_SSOTC	(*( SSC0_SSOTC_type *) 0xf010021cu)	/* Slave Select Output Timing Control Register */
#define SSC2_SSOTC	(*( SSC0_SSOTC_type *) 0xf010031cu)	/* Slave Select Output Timing Control Register */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int BC             : 4;
		/* const */ unsigned int PARE           : 1;
		/* const */ unsigned int PARTVAL        : 1;
		/* const */ unsigned int PARRVAL        : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int TE             : 1;
		/* const */ unsigned int RE             : 1;
		/* const */ unsigned int PE             : 1;
		/* const */ unsigned int BE             : 1;
		/* const */ unsigned int BSY            : 1;
		/* const */ unsigned int                : 19;
	} B;
	int I;
	unsigned int U;

} SSC0_STAT_type;
#define SSC0_STAT	(*( SSC0_STAT_type *) 0xf0100128u)	/* Status Register */
#define SSC1_STAT	(*( SSC0_STAT_type *) 0xf0100228u)	/* Status Register */
#define SSC2_STAT	(*( SSC0_STAT_type *) 0xf0100328u)	/* Status Register */

typedef volatile union
{
	struct
	{ 
		unsigned int TB_VALUE       : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} SSC0_TB_type;
#define SSC0_TB	(*( SSC0_TB_type *) 0xf0100120u)	/* Transmit Buffer Register */
#define SSC1_TB	(*( SSC0_TB_type *) 0xf0100220u)	/* Transmit Buffer Register */
#define SSC2_TB	(*( SSC0_TB_type *) 0xf0100320u)	/* Transmit Buffer Register */


/* MSC */
typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} MSC0_CLC_type;
#define MSC0_CLC	(*(MSC0_CLC_type*) 0xf0000800u)	/* MSC0 Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DCL            : 16;
		unsigned int DCH            : 16;
	} B;
	int I;
	unsigned int U;

} MSC0_DC_type;
#define MSC0_DC	(*(MSC0_DC_type*) 0xf0000820u)	/* Downstream Command Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DDL            : 16;
		unsigned int DDH            : 16;
	} B;
	int I;
	unsigned int U;

} MSC0_DD_type;
#define MSC0_DD	(*(MSC0_DD_type*) 0xf000081cu)	/* Downstream Data Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int TM             : 1;
		/* const */ unsigned int CP             : 1;
		/* const */ unsigned int DP             : 1;
		unsigned int NDBL           : 5;
		unsigned int NDBH           : 5;
		unsigned int ENSELL         : 1;
		unsigned int ENSELH         : 1;
		/* const */ unsigned int DSDIS          : 1;
		unsigned int NBC            : 6;
		unsigned int                : 2;
		unsigned int PPD            : 5;
		unsigned int                : 3;
	} B;
	int I;
	unsigned int U;

} MSC0_DSC_type;
#define MSC0_DSC	(*(MSC0_DSC_type*) 0xf0000814u)	/* Downstream Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SH0            : 2;
		unsigned int SH1            : 2;
		unsigned int SH2            : 2;
		unsigned int SH3            : 2;
		unsigned int SH4            : 2;
		unsigned int SH5            : 2;
		unsigned int SH6            : 2;
		unsigned int SH7            : 2;
		unsigned int SH8            : 2;
		unsigned int SH9            : 2;
		unsigned int SH10           : 2;
		unsigned int SH11           : 2;
		unsigned int SH12           : 2;
		unsigned int SH13           : 2;
		unsigned int SH14           : 2;
		unsigned int SH15           : 2;
	} B;
	int I;
	unsigned int U;

} MSC0_DSDSH_type;
#define MSC0_DSDSH	(*(MSC0_DSDSH_type*) 0xf0000828u)	/* Downstream Select Data Source High Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SL0            : 2;
		unsigned int SL1            : 2;
		unsigned int SL2            : 2;
		unsigned int SL3            : 2;
		unsigned int SL4            : 2;
		unsigned int SL5            : 2;
		unsigned int SL6            : 2;
		unsigned int SL7            : 2;
		unsigned int SL8            : 2;
		unsigned int SL9            : 2;
		unsigned int SL10           : 2;
		unsigned int SL11           : 2;
		unsigned int SL12           : 2;
		unsigned int SL13           : 2;
		unsigned int SL14           : 2;
		unsigned int SL15           : 2;
	} B;
	int I;
	unsigned int U;

} MSC0_DSDSL_type;
#define MSC0_DSDSL	(*(MSC0_DSDSL_type*) 0xf0000824u)	/* Downstream Select Data Source Low Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int PFC            : 4;
		unsigned int                : 4;
		unsigned int NPTF           : 4;
		unsigned int                : 4;
		/* const */ unsigned int DC             : 7;
		unsigned int                : 1;
		/* const */ unsigned int DFA            : 1;
		/* const */ unsigned int CFA            : 1;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} MSC0_DSS_type;
#define MSC0_DSS	(*(MSC0_DSS_type*) 0xf0000818u)	/* Downstream Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ENL0           : 1;
		unsigned int ENL1           : 1;
		unsigned int ENL2           : 1;
		unsigned int ENL3           : 1;
		unsigned int ENL4           : 1;
		unsigned int ENL5           : 1;
		unsigned int ENL6           : 1;
		unsigned int ENL7           : 1;
		unsigned int ENL8           : 1;
		unsigned int ENL9           : 1;
		unsigned int ENL10          : 1;
		unsigned int ENL11          : 1;
		unsigned int ENL12          : 1;
		unsigned int ENL13          : 1;
		unsigned int ENL14          : 1;
		unsigned int ENL15          : 1;
		unsigned int ENH0           : 1;
		unsigned int ENH1           : 1;
		unsigned int ENH2           : 1;
		unsigned int ENH3           : 1;
		unsigned int ENH4           : 1;
		unsigned int ENH5           : 1;
		unsigned int ENH6           : 1;
		unsigned int ENH7           : 1;
		unsigned int ENH8           : 1;
		unsigned int ENH9           : 1;
		unsigned int ENH10          : 1;
		unsigned int ENH11          : 1;
		unsigned int ENH12          : 1;
		unsigned int ENH13          : 1;
		unsigned int ENH14          : 1;
		unsigned int ENH15          : 1;
	} B;
	int I;
	unsigned int U;

} MSC0_ESR_type;
#define MSC0_ESR	(*(MSC0_ESR_type*) 0xf000082cu)	/* Emergency Stop Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STEP           : 10;
		unsigned int                : 1;
		unsigned int SM             : 1;
		unsigned int SC             : 2;
		unsigned int DM             : 2;
		/* const */ unsigned int RESULT         : 10;
		unsigned int                : 2;
		/* const */ unsigned int SUSACK         : 1;
		/* const */ unsigned int SUSREQ         : 1;
		unsigned int ENHW           : 1;
		unsigned int DISCLK         : 1;
	} B;
	int I;
	unsigned int U;

} MSC0_FDR_type;
#define MSC0_FDR	(*(MSC0_FDR_type*) 0xf000080cu)	/* MSC0 Fractional Divider Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int EDIP           : 2;
		unsigned int EDIE           : 2;
		unsigned int ECIP           : 2;
		unsigned int                : 1;
		unsigned int ECIE           : 1;
		unsigned int TFIP           : 2;
		unsigned int                : 1;
		unsigned int TFIE           : 1;
		unsigned int RDIP           : 2;
		unsigned int RDIE           : 2;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} MSC0_ICR_type;
#define MSC0_ICR	(*(MSC0_ICR_type*) 0xf0000840u)	/* Interrupt Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MODREV         : 8;
		/* const */ unsigned int MODTYPEq       : 8;
		/* const */ unsigned int MODNUM         : 16;
	} B;
	int I;
	unsigned int U;

} MSC0_ID_type;
#define MSC0_ID	(*(MSC0_ID_type*) 0xf0000808u)	/* Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CDEDI          : 1;
		unsigned int CDECI          : 1;
		unsigned int CDTFI          : 1;
		unsigned int CURDI          : 1;
		unsigned int CDP            : 1;
		unsigned int CCP            : 1;
		unsigned int CDDIS          : 1;
		unsigned int                : 9;
		unsigned int SDEDI          : 1;
		unsigned int SDECI          : 1;
		unsigned int SDTFI          : 1;
		unsigned int SURDI          : 1;
		unsigned int SDP            : 1;
		unsigned int SCP            : 1;
		unsigned int SDDIS          : 1;
		unsigned int                : 9;
	} B;
	int I;
	unsigned int U;

} MSC0_ISC_type;
#define MSC0_ISC	(*(MSC0_ISC_type*) 0xf0000848u)	/* Interrupt Set Clear Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int DEDI           : 1;
		/* const */ unsigned int DECI           : 1;
		/* const */ unsigned int DTFI           : 1;
		/* const */ unsigned int URDI           : 1;
		/* const */ unsigned int                : 28;
	} B;
	int I;
	unsigned int U;

} MSC0_ISR_type;
#define MSC0_ISR	(*(MSC0_ISR_type*) 0xf0000844u)	/* Interrupt Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CLP            : 1;
		unsigned int SLP            : 1;
		unsigned int CSLP           : 1;
		unsigned int ILP            : 1;
		unsigned int                : 4;
		unsigned int CLKCTRL        : 1;
		unsigned int CSL            : 2;
		unsigned int CSH            : 2;
		unsigned int CSC            : 2;
		unsigned int                : 1;
		unsigned int SDISEL         : 3;
		unsigned int                : 13;
	} B;
	int I;
	unsigned int U;

} MSC0_OCR_type;
#define MSC0_OCR	(*(MSC0_OCR_type*) 0xf000084cu)	/* Output Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} MSC0_SRC0_type;
#define MSC0_SRC0	(*(MSC0_SRC0_type*) 0xf00008fcu)	/* MSC0 Service Request Control Register 0  */
#define MSC0_SRC1	(*(MSC0_SRC0_type*) 0xf00008f8u)	/* MSC0 Service Request Control Register 1  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int DATA           : 8;
		unsigned int                : 8;
		/* const */ unsigned int V              : 1;
		/* const */ unsigned int P              : 1;
		unsigned int C              : 1;
		/* const */ unsigned int LABF           : 2;
		/* const */ unsigned int IPF            : 1;
		/* const */ unsigned int PERR           : 1;
		unsigned int                : 9;
	} B;
	int I;
	unsigned int U;

} MSC0_UD0_type;
#define MSC0_UD0	(*(MSC0_UD0_type*) 0xf0000830u)	/* Upstream Data Register 0  */
#define MSC0_UD1	(*(MSC0_UD0_type*) 0xf0000834u)	/* Upstream Data Register 1  */
#define MSC0_UD2	(*(MSC0_UD0_type*) 0xf0000838u)	/* Upstream Data Register 2  */
#define MSC0_UD3	(*(MSC0_UD0_type*) 0xf000083cu)	/* Upstream Data Register 3  */

typedef volatile union
{
	struct
	{ 
		unsigned int UFT            : 1;
		unsigned int URR            : 3;
		unsigned int PCTR           : 1;
		unsigned int                : 11;
		/* const */ unsigned int UC             : 5;
		unsigned int                : 11;
	} B;
	int I;
	unsigned int U;

} MSC0_USR_type;
#define MSC0_USR	(*(MSC0_USR_type*) 0xf0000810u)	/* Upstream Status Register  */


/* CAN */
typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} CAN_CLC_type;
#define CAN_CLC	(*(CAN_CLC_type*) 0xf0004000u)	/* CAN Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STEP           : 10;
		unsigned int                : 1;
		unsigned int SM             : 1;
		unsigned int SC             : 2;
		unsigned int DM             : 2;
		/* const */ unsigned int RESULT         : 10;
		unsigned int                : 2;
		/* const */ unsigned int SUSACK         : 1;
		/* const */ unsigned int SUSREQ         : 1;
		unsigned int ENHW           : 1;
		unsigned int DISCLK         : 1;
	} B;
	int I;
	unsigned int U;

} CAN_FDR_type;
#define CAN_FDR	(*(CAN_FDR_type*) 0xf000400cu)	/* CAN Fractional Divider Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int BEGIN          : 8;
		/* const */ unsigned int END            : 8;
		/* const */ unsigned int SIZE           : 8;
		/* const */ unsigned int EMPTY          : 1;
		/* const */ unsigned int                : 7;
	} B;
	int I;
	unsigned int U;

} CAN_LIST0_type;
#define CAN_LIST0	(*(CAN_LIST0_type*) 0xf0004100u)	/* List Register 0  */
#define CAN_LIST1	(*(CAN_LIST0_type*) 0xf0004104u)	/* List Register 1  */
#define CAN_LIST2	(*(CAN_LIST0_type*) 0xf0004108u)	/* List Register 2  */
#define CAN_LIST3	(*(CAN_LIST0_type*) 0xf000410cu)	/* List Register 3  */
#define CAN_LIST4	(*(CAN_LIST0_type*) 0xf0004110u)	/* List Register 4  */
#define CAN_LIST5	(*(CAN_LIST0_type*) 0xf0004114u)	/* List Register 5  */
#define CAN_LIST6	(*(CAN_LIST0_type*) 0xf0004118u)	/* List Register 6  */
#define CAN_LIST7	(*(CAN_LIST0_type*) 0xf000411cu)	/* List Register 7  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 12;
		unsigned int MPSEL          : 4;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} CAN_MCR_type;
#define CAN_MCR	(*(CAN_MCR_type*) 0xf00041c8u)	/* Module Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int IT             : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} CAN_MITR_type;
#define CAN_MITR	(*(CAN_MITR_type*) 0xf00041ccu)	/* Module Interrupt Trigger Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int AM             : 29;
		unsigned int MIDE           : 1;
		unsigned int                : 2;
	} B;
	int I;
	unsigned int U;

} CAN_MOAMR0_type;
#define CAN_MOAMR0	(*(CAN_MOAMR0_type*) 0xf000500cu)	/* Message Object 0 Acceptance Mask Register  */
#define CAN_MOAMR1	(*(CAN_MOAMR0_type*) 0xf000502cu)	/* Message Object 1 Acceptance Mask Register  */
#define CAN_MOAMR10	(*(CAN_MOAMR0_type*) 0xf000514cu)	/* Message Object 10 Acceptance Mask Register  */
#define CAN_MOAMR11	(*(CAN_MOAMR0_type*) 0xf000516cu)	/* Message Object 11 Acceptance Mask Register  */
#define CAN_MOAMR12	(*(CAN_MOAMR0_type*) 0xf000518cu)	/* Message Object 12 Acceptance Mask Register  */
#define CAN_MOAMR13	(*(CAN_MOAMR0_type*) 0xf00051acu)	/* Message Object 13 Acceptance Mask Register  */
#define CAN_MOAMR14	(*(CAN_MOAMR0_type*) 0xf00051ccu)	/* Message Object 14 Acceptance Mask Register  */
#define CAN_MOAMR15	(*(CAN_MOAMR0_type*) 0xf00051ecu)	/* Message Object 15 Acceptance Mask Register  */
#define CAN_MOAMR16	(*(CAN_MOAMR0_type*) 0xf000520cu)	/* Message Object 16 Acceptance Mask Register  */
#define CAN_MOAMR17	(*(CAN_MOAMR0_type*) 0xf000522cu)	/* Message Object 17 Acceptance Mask Register  */
#define CAN_MOAMR18	(*(CAN_MOAMR0_type*) 0xf000524cu)	/* Message Object 18 Acceptance Mask Register  */
#define CAN_MOAMR19	(*(CAN_MOAMR0_type*) 0xf000526cu)	/* Message Object 19 Acceptance Mask Register  */
#define CAN_MOAMR2	(*(CAN_MOAMR0_type*) 0xf000504cu)	/* Message Object 2 Acceptance Mask Register  */
#define CAN_MOAMR20	(*(CAN_MOAMR0_type*) 0xf000528cu)	/* Message Object 20 Acceptance Mask Register  */
#define CAN_MOAMR21	(*(CAN_MOAMR0_type*) 0xf00052acu)	/* Message Object 21 Acceptance Mask Register  */
#define CAN_MOAMR22	(*(CAN_MOAMR0_type*) 0xf00052ccu)	/* Message Object 22 Acceptance Mask Register  */
#define CAN_MOAMR23	(*(CAN_MOAMR0_type*) 0xf00052ecu)	/* Message Object 23 Acceptance Mask Register  */
#define CAN_MOAMR24	(*(CAN_MOAMR0_type*) 0xf000530cu)	/* Message Object 24 Acceptance Mask Register  */
#define CAN_MOAMR25	(*(CAN_MOAMR0_type*) 0xf000532cu)	/* Message Object 25 Acceptance Mask Register  */
#define CAN_MOAMR26	(*(CAN_MOAMR0_type*) 0xf000534cu)	/* Message Object 26 Acceptance Mask Register  */
#define CAN_MOAMR27	(*(CAN_MOAMR0_type*) 0xf000536cu)	/* Message Object 27 Acceptance Mask Register  */
#define CAN_MOAMR28	(*(CAN_MOAMR0_type*) 0xf000538cu)	/* Message Object 28 Acceptance Mask Register  */
#define CAN_MOAMR29	(*(CAN_MOAMR0_type*) 0xf00053acu)	/* Message Object 29 Acceptance Mask Register  */
#define CAN_MOAMR3	(*(CAN_MOAMR0_type*) 0xf000506cu)	/* Message Object 3 Acceptance Mask Register  */
#define CAN_MOAMR30	(*(CAN_MOAMR0_type*) 0xf00053ccu)	/* Message Object 30 Acceptance Mask Register  */
#define CAN_MOAMR31	(*(CAN_MOAMR0_type*) 0xf00053ecu)	/* Message Object 31 Acceptance Mask Register  */
#define CAN_MOAMR32	(*(CAN_MOAMR0_type*) 0xf000540cu)	/* Message Object 32 Acceptance Mask Register  */
#define CAN_MOAMR33	(*(CAN_MOAMR0_type*) 0xf000542cu)	/* Message Object 33 Acceptance Mask Register  */
#define CAN_MOAMR34	(*(CAN_MOAMR0_type*) 0xf000544cu)	/* Message Object 34 Acceptance Mask Register  */
#define CAN_MOAMR35	(*(CAN_MOAMR0_type*) 0xf000546cu)	/* Message Object 35 Acceptance Mask Register  */
#define CAN_MOAMR36	(*(CAN_MOAMR0_type*) 0xf000548cu)	/* Message Object 36 Acceptance Mask Register  */
#define CAN_MOAMR37	(*(CAN_MOAMR0_type*) 0xf00054acu)	/* Message Object 37 Acceptance Mask Register  */
#define CAN_MOAMR38	(*(CAN_MOAMR0_type*) 0xf00054ccu)	/* Message Object 38 Acceptance Mask Register  */
#define CAN_MOAMR39	(*(CAN_MOAMR0_type*) 0xf00054ecu)	/* Message Object 39 Acceptance Mask Register  */
#define CAN_MOAMR4	(*(CAN_MOAMR0_type*) 0xf000508cu)	/* Message Object 4 Acceptance Mask Register  */
#define CAN_MOAMR40	(*(CAN_MOAMR0_type*) 0xf000550cu)	/* Message Object 40 Acceptance Mask Register  */
#define CAN_MOAMR41	(*(CAN_MOAMR0_type*) 0xf000552cu)	/* Message Object 41 Acceptance Mask Register  */
#define CAN_MOAMR42	(*(CAN_MOAMR0_type*) 0xf000554cu)	/* Message Object 42 Acceptance Mask Register  */
#define CAN_MOAMR43	(*(CAN_MOAMR0_type*) 0xf000556cu)	/* Message Object 43 Acceptance Mask Register  */
#define CAN_MOAMR44	(*(CAN_MOAMR0_type*) 0xf000558cu)	/* Message Object 44 Acceptance Mask Register  */
#define CAN_MOAMR45	(*(CAN_MOAMR0_type*) 0xf00055acu)	/* Message Object 45 Acceptance Mask Register  */
#define CAN_MOAMR46	(*(CAN_MOAMR0_type*) 0xf00055ccu)	/* Message Object 46 Acceptance Mask Register  */
#define CAN_MOAMR47	(*(CAN_MOAMR0_type*) 0xf00055ecu)	/* Message Object 47 Acceptance Mask Register  */
#define CAN_MOAMR48	(*(CAN_MOAMR0_type*) 0xf000560cu)	/* Message Object 48 Acceptance Mask Register  */
#define CAN_MOAMR49	(*(CAN_MOAMR0_type*) 0xf000562cu)	/* Message Object 49 Acceptance Mask Register  */
#define CAN_MOAMR5	(*(CAN_MOAMR0_type*) 0xf00050acu)	/* Message Object 5 Acceptance Mask Register  */
#define CAN_MOAMR50	(*(CAN_MOAMR0_type*) 0xf000564cu)	/* Message Object 50 Acceptance Mask Register  */
#define CAN_MOAMR51	(*(CAN_MOAMR0_type*) 0xf000566cu)	/* Message Object 51 Acceptance Mask Register  */
#define CAN_MOAMR52	(*(CAN_MOAMR0_type*) 0xf000568cu)	/* Message Object 52 Acceptance Mask Register  */
#define CAN_MOAMR53	(*(CAN_MOAMR0_type*) 0xf00056acu)	/* Message Object 53 Acceptance Mask Register  */
#define CAN_MOAMR54	(*(CAN_MOAMR0_type*) 0xf00056ccu)	/* Message Object 54 Acceptance Mask Register  */
#define CAN_MOAMR55	(*(CAN_MOAMR0_type*) 0xf00056ecu)	/* Message Object 55 Acceptance Mask Register  */
#define CAN_MOAMR56	(*(CAN_MOAMR0_type*) 0xf000570cu)	/* Message Object 56 Acceptance Mask Register  */
#define CAN_MOAMR57	(*(CAN_MOAMR0_type*) 0xf000572cu)	/* Message Object 57 Acceptance Mask Register  */
#define CAN_MOAMR58	(*(CAN_MOAMR0_type*) 0xf000574cu)	/* Message Object 58 Acceptance Mask Register  */
#define CAN_MOAMR59	(*(CAN_MOAMR0_type*) 0xf000576cu)	/* Message Object 59 Acceptance Mask Register  */
#define CAN_MOAMR6	(*(CAN_MOAMR0_type*) 0xf00050ccu)	/* Message Object 6 Acceptance Mask Register  */
#define CAN_MOAMR60	(*(CAN_MOAMR0_type*) 0xf000578cu)	/* Message Object 60 Acceptance Mask Register  */
#define CAN_MOAMR61	(*(CAN_MOAMR0_type*) 0xf00057acu)	/* Message Object 61 Acceptance Mask Register  */
#define CAN_MOAMR62	(*(CAN_MOAMR0_type*) 0xf00057ccu)	/* Message Object 62 Acceptance Mask Register  */
#define CAN_MOAMR63	(*(CAN_MOAMR0_type*) 0xf00057ecu)	/* Message Object 63 Acceptance Mask Register  */
#define CAN_MOAMR7	(*(CAN_MOAMR0_type*) 0xf00050ecu)	/* Message Object 7 Acceptance Mask Register  */
#define CAN_MOAMR8	(*(CAN_MOAMR0_type*) 0xf000510cu)	/* Message Object 8 Acceptance Mask Register  */
#define CAN_MOAMR9	(*(CAN_MOAMR0_type*) 0xf000512cu)	/* Message Object 9 Acceptance Mask Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ID             : 29;
		unsigned int IDE            : 1;
		unsigned int PRI            : 2;
	} B;
	int I;
	unsigned int U;

} CAN_MOAR0_type;
#define CAN_MOAR0	(*(CAN_MOAR0_type*) 0xf0005018u)	/* Message Object 0 Arbitration Register  */
#define CAN_MOAR1	(*(CAN_MOAR0_type*) 0xf0005038u)	/* Message Object 1 Arbitration Register  */
#define CAN_MOAR10	(*(CAN_MOAR0_type*) 0xf0005158u)	/* Message Object 10 Arbitration Register  */
#define CAN_MOAR11	(*(CAN_MOAR0_type*) 0xf0005178u)	/* Message Object 11 Arbitration Register  */
#define CAN_MOAR12	(*(CAN_MOAR0_type*) 0xf0005198u)	/* Message Object 12 Arbitration Register  */
#define CAN_MOAR13	(*(CAN_MOAR0_type*) 0xf00051b8u)	/* Message Object 13 Arbitration Register  */
#define CAN_MOAR14	(*(CAN_MOAR0_type*) 0xf00051d8u)	/* Message Object 14 Arbitration Register  */
#define CAN_MOAR15	(*(CAN_MOAR0_type*) 0xf00051f8u)	/* Message Object 15 Arbitration Register  */
#define CAN_MOAR16	(*(CAN_MOAR0_type*) 0xf0005218u)	/* Message Object 16 Arbitration Register  */
#define CAN_MOAR17	(*(CAN_MOAR0_type*) 0xf0005238u)	/* Message Object 17 Arbitration Register  */
#define CAN_MOAR18	(*(CAN_MOAR0_type*) 0xf0005258u)	/* Message Object 18 Arbitration Register  */
#define CAN_MOAR19	(*(CAN_MOAR0_type*) 0xf0005278u)	/* Message Object 19 Arbitration Register  */
#define CAN_MOAR2	(*(CAN_MOAR0_type*) 0xf0005058u)	/* Message Object 2 Arbitration Register  */
#define CAN_MOAR20	(*(CAN_MOAR0_type*) 0xf0005298u)	/* Message Object 20 Arbitration Register  */
#define CAN_MOAR21	(*(CAN_MOAR0_type*) 0xf00052b8u)	/* Message Object 21 Arbitration Register  */
#define CAN_MOAR22	(*(CAN_MOAR0_type*) 0xf00052d8u)	/* Message Object 22 Arbitration Register  */
#define CAN_MOAR23	(*(CAN_MOAR0_type*) 0xf00052f8u)	/* Message Object 23 Arbitration Register  */
#define CAN_MOAR24	(*(CAN_MOAR0_type*) 0xf0005318u)	/* Message Object 24 Arbitration Register  */
#define CAN_MOAR25	(*(CAN_MOAR0_type*) 0xf0005338u)	/* Message Object 25 Arbitration Register  */
#define CAN_MOAR26	(*(CAN_MOAR0_type*) 0xf0005358u)	/* Message Object 26 Arbitration Register  */
#define CAN_MOAR27	(*(CAN_MOAR0_type*) 0xf0005378u)	/* Message Object 27 Arbitration Register  */
#define CAN_MOAR28	(*(CAN_MOAR0_type*) 0xf0005398u)	/* Message Object 28 Arbitration Register  */
#define CAN_MOAR29	(*(CAN_MOAR0_type*) 0xf00053b8u)	/* Message Object 29 Arbitration Register  */
#define CAN_MOAR3	(*(CAN_MOAR0_type*) 0xf0005078u)	/* Message Object 3 Arbitration Register  */
#define CAN_MOAR30	(*(CAN_MOAR0_type*) 0xf00053d8u)	/* Message Object 30 Arbitration Register  */
#define CAN_MOAR31	(*(CAN_MOAR0_type*) 0xf00053f8u)	/* Message Object 31 Arbitration Register  */
#define CAN_MOAR32	(*(CAN_MOAR0_type*) 0xf0005418u)	/* Message Object 32 Arbitration Register  */
#define CAN_MOAR33	(*(CAN_MOAR0_type*) 0xf0005438u)	/* Message Object 33 Arbitration Register  */
#define CAN_MOAR34	(*(CAN_MOAR0_type*) 0xf0005458u)	/* Message Object 34 Arbitration Register  */
#define CAN_MOAR35	(*(CAN_MOAR0_type*) 0xf0005478u)	/* Message Object 35 Arbitration Register  */
#define CAN_MOAR36	(*(CAN_MOAR0_type*) 0xf0005498u)	/* Message Object 36 Arbitration Register  */
#define CAN_MOAR37	(*(CAN_MOAR0_type*) 0xf00054b8u)	/* Message Object 37 Arbitration Register  */
#define CAN_MOAR38	(*(CAN_MOAR0_type*) 0xf00054d8u)	/* Message Object 38 Arbitration Register  */
#define CAN_MOAR39	(*(CAN_MOAR0_type*) 0xf00054f8u)	/* Message Object 39 Arbitration Register  */
#define CAN_MOAR4	(*(CAN_MOAR0_type*) 0xf0005098u)	/* Message Object 4 Arbitration Register  */
#define CAN_MOAR40	(*(CAN_MOAR0_type*) 0xf0005518u)	/* Message Object 40 Arbitration Register  */
#define CAN_MOAR41	(*(CAN_MOAR0_type*) 0xf0005538u)	/* Message Object 41 Arbitration Register  */
#define CAN_MOAR42	(*(CAN_MOAR0_type*) 0xf0005558u)	/* Message Object 42 Arbitration Register  */
#define CAN_MOAR43	(*(CAN_MOAR0_type*) 0xf0005578u)	/* Message Object 43 Arbitration Register  */
#define CAN_MOAR44	(*(CAN_MOAR0_type*) 0xf0005598u)	/* Message Object 44 Arbitration Register  */
#define CAN_MOAR45	(*(CAN_MOAR0_type*) 0xf00055b8u)	/* Message Object 45 Arbitration Register  */
#define CAN_MOAR46	(*(CAN_MOAR0_type*) 0xf00055d8u)	/* Message Object 46 Arbitration Register  */
#define CAN_MOAR47	(*(CAN_MOAR0_type*) 0xf00055f8u)	/* Message Object 47 Arbitration Register  */
#define CAN_MOAR48	(*(CAN_MOAR0_type*) 0xf0005618u)	/* Message Object 48 Arbitration Register  */
#define CAN_MOAR49	(*(CAN_MOAR0_type*) 0xf0005638u)	/* Message Object 49 Arbitration Register  */
#define CAN_MOAR5	(*(CAN_MOAR0_type*) 0xf00050b8u)	/* Message Object 5 Arbitration Register  */
#define CAN_MOAR50	(*(CAN_MOAR0_type*) 0xf0005658u)	/* Message Object 50 Arbitration Register  */
#define CAN_MOAR51	(*(CAN_MOAR0_type*) 0xf0005678u)	/* Message Object 51 Arbitration Register  */
#define CAN_MOAR52	(*(CAN_MOAR0_type*) 0xf0005698u)	/* Message Object 52 Arbitration Register  */
#define CAN_MOAR53	(*(CAN_MOAR0_type*) 0xf00056b8u)	/* Message Object 53 Arbitration Register  */
#define CAN_MOAR54	(*(CAN_MOAR0_type*) 0xf00056d8u)	/* Message Object 54 Arbitration Register  */
#define CAN_MOAR55	(*(CAN_MOAR0_type*) 0xf00056f8u)	/* Message Object 55 Arbitration Register  */
#define CAN_MOAR56	(*(CAN_MOAR0_type*) 0xf0005718u)	/* Message Object 56 Arbitration Register  */
#define CAN_MOAR57	(*(CAN_MOAR0_type*) 0xf0005738u)	/* Message Object 57 Arbitration Register  */
#define CAN_MOAR58	(*(CAN_MOAR0_type*) 0xf0005758u)	/* Message Object 58 Arbitration Register  */
#define CAN_MOAR59	(*(CAN_MOAR0_type*) 0xf0005778u)	/* Message Object 59 Arbitration Register  */
#define CAN_MOAR6	(*(CAN_MOAR0_type*) 0xf00050d8u)	/* Message Object 6 Arbitration Register  */
#define CAN_MOAR60	(*(CAN_MOAR0_type*) 0xf0005798u)	/* Message Object 60 Arbitration Register  */
#define CAN_MOAR61	(*(CAN_MOAR0_type*) 0xf00057b8u)	/* Message Object 61 Arbitration Register  */
#define CAN_MOAR62	(*(CAN_MOAR0_type*) 0xf00057d8u)	/* Message Object 62 Arbitration Register  */
#define CAN_MOAR63	(*(CAN_MOAR0_type*) 0xf00057f8u)	/* Message Object 63 Arbitration Register  */
#define CAN_MOAR7	(*(CAN_MOAR0_type*) 0xf00050f8u)	/* Message Object 7 Arbitration Register  */
#define CAN_MOAR8	(*(CAN_MOAR0_type*) 0xf0005118u)	/* Message Object 8 Arbitration Register  */
#define CAN_MOAR9	(*(CAN_MOAR0_type*) 0xf0005138u)	/* Message Object 9 Arbitration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int RESRXPND       : 1;
		unsigned int RESTXPND       : 1;
		unsigned int RESRXUPD       : 1;
		unsigned int RESNEWDAT      : 1;
		unsigned int RESMSGLST      : 1;
		unsigned int RESMSGVAL      : 1;
		unsigned int RESRTSEL       : 1;
		unsigned int RESRXEN        : 1;
		unsigned int RESTXRQ        : 1;
		unsigned int RESTXEN0       : 1;
		unsigned int RESTXEN1       : 1;
		unsigned int RESDIR         : 1;
		unsigned int                : 4;
		unsigned int SETRXPND       : 1;
		unsigned int SETTXPND       : 1;
		unsigned int SETRXUPD       : 1;
		unsigned int SETNEWDAT      : 1;
		unsigned int SETMSGLST      : 1;
		unsigned int SETMSGVAL      : 1;
		unsigned int SETRTSEL       : 1;
		unsigned int SETRXEN        : 1;
		unsigned int SETTXRQ        : 1;
		unsigned int SETTXEN0       : 1;
		unsigned int SETTXEN1       : 1;
		unsigned int SETDIR         : 1;
		unsigned int                : 4;
	} B;
	int I;
	unsigned int U;

} CAN_MOCTR0_type;
#define CAN_MOCTR0	(*(CAN_MOCTR0_type*) 0xf000501cu)	/* Message Object 0 Control Register  */
#define CAN_MOCTR1	(*(CAN_MOCTR0_type*) 0xf000503cu)	/* Message Object 1 Control Register  */
#define CAN_MOCTR10	(*(CAN_MOCTR0_type*) 0xf000515cu)	/* Message Object 10 Control Register  */
#define CAN_MOCTR11	(*(CAN_MOCTR0_type*) 0xf000517cu)	/* Message Object 11 Control Register  */
#define CAN_MOCTR12	(*(CAN_MOCTR0_type*) 0xf000519cu)	/* Message Object 12 Control Register  */
#define CAN_MOCTR13	(*(CAN_MOCTR0_type*) 0xf00051bcu)	/* Message Object 13 Control Register  */
#define CAN_MOCTR14	(*(CAN_MOCTR0_type*) 0xf00051dcu)	/* Message Object 14 Control Register  */
#define CAN_MOCTR15	(*(CAN_MOCTR0_type*) 0xf00051fcu)	/* Message Object 15 Control Register  */
#define CAN_MOCTR16	(*(CAN_MOCTR0_type*) 0xf000521cu)	/* Message Object 16 Control Register  */
#define CAN_MOCTR17	(*(CAN_MOCTR0_type*) 0xf000523cu)	/* Message Object 17 Control Register  */
#define CAN_MOCTR18	(*(CAN_MOCTR0_type*) 0xf000525cu)	/* Message Object 18 Control Register  */
#define CAN_MOCTR19	(*(CAN_MOCTR0_type*) 0xf000527cu)	/* Message Object 19 Control Register  */
#define CAN_MOCTR2	(*(CAN_MOCTR0_type*) 0xf000505cu)	/* Message Object 2 Control Register  */
#define CAN_MOCTR20	(*(CAN_MOCTR0_type*) 0xf000529cu)	/* Message Object 20 Control Register  */
#define CAN_MOCTR21	(*(CAN_MOCTR0_type*) 0xf00052bcu)	/* Message Object 21 Control Register  */
#define CAN_MOCTR22	(*(CAN_MOCTR0_type*) 0xf00052dcu)	/* Message Object 22 Control Register  */
#define CAN_MOCTR23	(*(CAN_MOCTR0_type*) 0xf00052fcu)	/* Message Object 23 Control Register  */
#define CAN_MOCTR24	(*(CAN_MOCTR0_type*) 0xf000531cu)	/* Message Object 24 Control Register  */
#define CAN_MOCTR25	(*(CAN_MOCTR0_type*) 0xf000533cu)	/* Message Object 25 Control Register  */
#define CAN_MOCTR26	(*(CAN_MOCTR0_type*) 0xf000535cu)	/* Message Object 26 Control Register  */
#define CAN_MOCTR27	(*(CAN_MOCTR0_type*) 0xf000537cu)	/* Message Object 27 Control Register  */
#define CAN_MOCTR28	(*(CAN_MOCTR0_type*) 0xf000539cu)	/* Message Object 28 Control Register  */
#define CAN_MOCTR29	(*(CAN_MOCTR0_type*) 0xf00053bcu)	/* Message Object 29 Control Register  */
#define CAN_MOCTR3	(*(CAN_MOCTR0_type*) 0xf000507cu)	/* Message Object 3 Control Register  */
#define CAN_MOCTR30	(*(CAN_MOCTR0_type*) 0xf00053dcu)	/* Message Object 30 Control Register  */
#define CAN_MOCTR31	(*(CAN_MOCTR0_type*) 0xf00053fcu)	/* Message Object 31 Control Register  */
#define CAN_MOCTR32	(*(CAN_MOCTR0_type*) 0xf000541cu)	/* Message Object 32 Control Register  */
#define CAN_MOCTR33	(*(CAN_MOCTR0_type*) 0xf000543cu)	/* Message Object 33 Control Register  */
#define CAN_MOCTR34	(*(CAN_MOCTR0_type*) 0xf000545cu)	/* Message Object 34 Control Register  */
#define CAN_MOCTR35	(*(CAN_MOCTR0_type*) 0xf000547cu)	/* Message Object 35 Control Register  */
#define CAN_MOCTR36	(*(CAN_MOCTR0_type*) 0xf000549cu)	/* Message Object 36 Control Register  */
#define CAN_MOCTR37	(*(CAN_MOCTR0_type*) 0xf00054bcu)	/* Message Object 37 Control Register  */
#define CAN_MOCTR38	(*(CAN_MOCTR0_type*) 0xf00054dcu)	/* Message Object 38 Control Register  */
#define CAN_MOCTR39	(*(CAN_MOCTR0_type*) 0xf00054fcu)	/* Message Object 39 Control Register  */
#define CAN_MOCTR4	(*(CAN_MOCTR0_type*) 0xf000509cu)	/* Message Object 4 Control Register  */
#define CAN_MOCTR40	(*(CAN_MOCTR0_type*) 0xf000551cu)	/* Message Object 40 Control Register  */
#define CAN_MOCTR41	(*(CAN_MOCTR0_type*) 0xf000553cu)	/* Message Object 41 Control Register  */
#define CAN_MOCTR42	(*(CAN_MOCTR0_type*) 0xf000555cu)	/* Message Object 42 Control Register  */
#define CAN_MOCTR43	(*(CAN_MOCTR0_type*) 0xf000557cu)	/* Message Object 43 Control Register  */
#define CAN_MOCTR44	(*(CAN_MOCTR0_type*) 0xf000559cu)	/* Message Object 44 Control Register  */
#define CAN_MOCTR45	(*(CAN_MOCTR0_type*) 0xf00055bcu)	/* Message Object 45 Control Register  */
#define CAN_MOCTR46	(*(CAN_MOCTR0_type*) 0xf00055dcu)	/* Message Object 46 Control Register  */
#define CAN_MOCTR47	(*(CAN_MOCTR0_type*) 0xf00055fcu)	/* Message Object 47 Control Register  */
#define CAN_MOCTR48	(*(CAN_MOCTR0_type*) 0xf000561cu)	/* Message Object 48 Control Register  */
#define CAN_MOCTR49	(*(CAN_MOCTR0_type*) 0xf000563cu)	/* Message Object 49 Control Register  */
#define CAN_MOCTR5	(*(CAN_MOCTR0_type*) 0xf00050bcu)	/* Message Object 5 Control Register  */
#define CAN_MOCTR50	(*(CAN_MOCTR0_type*) 0xf000565cu)	/* Message Object 50 Control Register  */
#define CAN_MOCTR51	(*(CAN_MOCTR0_type*) 0xf000567cu)	/* Message Object 51 Control Register  */
#define CAN_MOCTR52	(*(CAN_MOCTR0_type*) 0xf000569cu)	/* Message Object 52 Control Register  */
#define CAN_MOCTR53	(*(CAN_MOCTR0_type*) 0xf00056bcu)	/* Message Object 53 Control Register  */
#define CAN_MOCTR54	(*(CAN_MOCTR0_type*) 0xf00056dcu)	/* Message Object 54 Control Register  */
#define CAN_MOCTR55	(*(CAN_MOCTR0_type*) 0xf00056fcu)	/* Message Object 55 Control Register  */
#define CAN_MOCTR56	(*(CAN_MOCTR0_type*) 0xf000571cu)	/* Message Object 56 Control Register  */
#define CAN_MOCTR57	(*(CAN_MOCTR0_type*) 0xf000573cu)	/* Message Object 57 Control Register  */
#define CAN_MOCTR58	(*(CAN_MOCTR0_type*) 0xf000575cu)	/* Message Object 58 Control Register  */
#define CAN_MOCTR59	(*(CAN_MOCTR0_type*) 0xf000577cu)	/* Message Object 59 Control Register  */
#define CAN_MOCTR6	(*(CAN_MOCTR0_type*) 0xf00050dcu)	/* Message Object 6 Control Register  */
#define CAN_MOCTR60	(*(CAN_MOCTR0_type*) 0xf000579cu)	/* Message Object 60 Control Register  */
#define CAN_MOCTR61	(*(CAN_MOCTR0_type*) 0xf00057bcu)	/* Message Object 61 Control Register  */
#define CAN_MOCTR62	(*(CAN_MOCTR0_type*) 0xf00057dcu)	/* Message Object 62 Control Register  */
#define CAN_MOCTR63	(*(CAN_MOCTR0_type*) 0xf00057fcu)	/* Message Object 63 Control Register  */
#define CAN_MOCTR7	(*(CAN_MOCTR0_type*) 0xf00050fcu)	/* Message Object 7 Control Register  */
#define CAN_MOCTR8	(*(CAN_MOCTR0_type*) 0xf000511cu)	/* Message Object 8 Control Register  */
#define CAN_MOCTR9	(*(CAN_MOCTR0_type*) 0xf000513cu)	/* Message Object 9 Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DB4            : 8;
		unsigned int DB5            : 8;
		unsigned int DB6            : 8;
		unsigned int DB7            : 8;
	} B;
	int I;
	unsigned int U;

} CAN_MODATAH0_type;
#define CAN_MODATAH0	(*(CAN_MODATAH0_type*) 0xf0005014u)	/* Message Object 0 Data Register High  */
#define CAN_MODATAH1	(*(CAN_MODATAH0_type*) 0xf0005034u)	/* Message Object 1 Data Register High  */
#define CAN_MODATAH10	(*(CAN_MODATAH0_type*) 0xf0005154u)	/* Message Object 10 Data Register High  */
#define CAN_MODATAH11	(*(CAN_MODATAH0_type*) 0xf0005174u)	/* Message Object 11 Data Register High  */
#define CAN_MODATAH12	(*(CAN_MODATAH0_type*) 0xf0005194u)	/* Message Object 12 Data Register High  */
#define CAN_MODATAH13	(*(CAN_MODATAH0_type*) 0xf00051b4u)	/* Message Object 13 Data Register High  */
#define CAN_MODATAH14	(*(CAN_MODATAH0_type*) 0xf00051d4u)	/* Message Object 14 Data Register High  */
#define CAN_MODATAH15	(*(CAN_MODATAH0_type*) 0xf00051f4u)	/* Message Object 15 Data Register High  */
#define CAN_MODATAH16	(*(CAN_MODATAH0_type*) 0xf0005214u)	/* Message Object 16 Data Register High  */
#define CAN_MODATAH17	(*(CAN_MODATAH0_type*) 0xf0005234u)	/* Message Object 17 Data Register High  */
#define CAN_MODATAH18	(*(CAN_MODATAH0_type*) 0xf0005254u)	/* Message Object 18 Data Register High  */
#define CAN_MODATAH19	(*(CAN_MODATAH0_type*) 0xf0005274u)	/* Message Object 19 Data Register High  */
#define CAN_MODATAH2	(*(CAN_MODATAH0_type*) 0xf0005054u)	/* Message Object 2 Data Register High  */
#define CAN_MODATAH20	(*(CAN_MODATAH0_type*) 0xf0005294u)	/* Message Object 20 Data Register High  */
#define CAN_MODATAH21	(*(CAN_MODATAH0_type*) 0xf00052b4u)	/* Message Object 21 Data Register High  */
#define CAN_MODATAH22	(*(CAN_MODATAH0_type*) 0xf00052d4u)	/* Message Object 22 Data Register High  */
#define CAN_MODATAH23	(*(CAN_MODATAH0_type*) 0xf00052f4u)	/* Message Object 23 Data Register High  */
#define CAN_MODATAH24	(*(CAN_MODATAH0_type*) 0xf0005314u)	/* Message Object 24 Data Register High  */
#define CAN_MODATAH25	(*(CAN_MODATAH0_type*) 0xf0005334u)	/* Message Object 25 Data Register High  */
#define CAN_MODATAH26	(*(CAN_MODATAH0_type*) 0xf0005354u)	/* Message Object 26 Data Register High  */
#define CAN_MODATAH27	(*(CAN_MODATAH0_type*) 0xf0005374u)	/* Message Object 27 Data Register High  */
#define CAN_MODATAH28	(*(CAN_MODATAH0_type*) 0xf0005394u)	/* Message Object 28 Data Register High  */
#define CAN_MODATAH29	(*(CAN_MODATAH0_type*) 0xf00053b4u)	/* Message Object 29 Data Register High  */
#define CAN_MODATAH3	(*(CAN_MODATAH0_type*) 0xf0005074u)	/* Message Object 3 Data Register High  */
#define CAN_MODATAH30	(*(CAN_MODATAH0_type*) 0xf00053d4u)	/* Message Object 30 Data Register High  */
#define CAN_MODATAH31	(*(CAN_MODATAH0_type*) 0xf00053f4u)	/* Message Object 31 Data Register High  */
#define CAN_MODATAH32	(*(CAN_MODATAH0_type*) 0xf0005414u)	/* Message Object 32 Data Register High  */
#define CAN_MODATAH33	(*(CAN_MODATAH0_type*) 0xf0005434u)	/* Message Object 33 Data Register High  */
#define CAN_MODATAH34	(*(CAN_MODATAH0_type*) 0xf0005454u)	/* Message Object 34 Data Register High  */
#define CAN_MODATAH35	(*(CAN_MODATAH0_type*) 0xf0005474u)	/* Message Object 35 Data Register High  */
#define CAN_MODATAH36	(*(CAN_MODATAH0_type*) 0xf0005494u)	/* Message Object 36 Data Register High  */
#define CAN_MODATAH37	(*(CAN_MODATAH0_type*) 0xf00054b4u)	/* Message Object 37 Data Register High  */
#define CAN_MODATAH38	(*(CAN_MODATAH0_type*) 0xf00054d4u)	/* Message Object 38 Data Register High  */
#define CAN_MODATAH39	(*(CAN_MODATAH0_type*) 0xf00054f4u)	/* Message Object 39 Data Register High  */
#define CAN_MODATAH4	(*(CAN_MODATAH0_type*) 0xf0005094u)	/* Message Object 4 Data Register High  */
#define CAN_MODATAH40	(*(CAN_MODATAH0_type*) 0xf0005514u)	/* Message Object 40 Data Register High  */
#define CAN_MODATAH41	(*(CAN_MODATAH0_type*) 0xf0005534u)	/* Message Object 41 Data Register High  */
#define CAN_MODATAH42	(*(CAN_MODATAH0_type*) 0xf0005554u)	/* Message Object 42 Data Register High  */
#define CAN_MODATAH43	(*(CAN_MODATAH0_type*) 0xf0005574u)	/* Message Object 43 Data Register High  */
#define CAN_MODATAH44	(*(CAN_MODATAH0_type*) 0xf0005594u)	/* Message Object 44 Data Register High  */
#define CAN_MODATAH45	(*(CAN_MODATAH0_type*) 0xf00055b4u)	/* Message Object 45 Data Register High  */
#define CAN_MODATAH46	(*(CAN_MODATAH0_type*) 0xf00055d4u)	/* Message Object 46 Data Register High  */
#define CAN_MODATAH47	(*(CAN_MODATAH0_type*) 0xf00055f4u)	/* Message Object 47 Data Register High  */
#define CAN_MODATAH48	(*(CAN_MODATAH0_type*) 0xf0005614u)	/* Message Object 48 Data Register High  */
#define CAN_MODATAH49	(*(CAN_MODATAH0_type*) 0xf0005634u)	/* Message Object 49 Data Register High  */
#define CAN_MODATAH5	(*(CAN_MODATAH0_type*) 0xf00050b4u)	/* Message Object 5 Data Register High  */
#define CAN_MODATAH50	(*(CAN_MODATAH0_type*) 0xf0005654u)	/* Message Object 50 Data Register High  */
#define CAN_MODATAH51	(*(CAN_MODATAH0_type*) 0xf0005674u)	/* Message Object 51 Data Register High  */
#define CAN_MODATAH52	(*(CAN_MODATAH0_type*) 0xf0005694u)	/* Message Object 52 Data Register High  */
#define CAN_MODATAH53	(*(CAN_MODATAH0_type*) 0xf00056b4u)	/* Message Object 53 Data Register High  */
#define CAN_MODATAH54	(*(CAN_MODATAH0_type*) 0xf00056d4u)	/* Message Object 54 Data Register High  */
#define CAN_MODATAH55	(*(CAN_MODATAH0_type*) 0xf00056f4u)	/* Message Object 55 Data Register High  */
#define CAN_MODATAH56	(*(CAN_MODATAH0_type*) 0xf0005714u)	/* Message Object 56 Data Register High  */
#define CAN_MODATAH57	(*(CAN_MODATAH0_type*) 0xf0005734u)	/* Message Object 57 Data Register High  */
#define CAN_MODATAH58	(*(CAN_MODATAH0_type*) 0xf0005754u)	/* Message Object 58 Data Register High  */
#define CAN_MODATAH59	(*(CAN_MODATAH0_type*) 0xf0005774u)	/* Message Object 59 Data Register High  */
#define CAN_MODATAH6	(*(CAN_MODATAH0_type*) 0xf00050d4u)	/* Message Object 6 Data Register High  */
#define CAN_MODATAH60	(*(CAN_MODATAH0_type*) 0xf0005794u)	/* Message Object 60 Data Register High  */
#define CAN_MODATAH61	(*(CAN_MODATAH0_type*) 0xf00057b4u)	/* Message Object 61 Data Register High  */
#define CAN_MODATAH62	(*(CAN_MODATAH0_type*) 0xf00057d4u)	/* Message Object 62 Data Register High  */
#define CAN_MODATAH63	(*(CAN_MODATAH0_type*) 0xf00057f4u)	/* Message Object 63 Data Register High  */
#define CAN_MODATAH7	(*(CAN_MODATAH0_type*) 0xf00050f4u)	/* Message Object 7 Data Register High  */
#define CAN_MODATAH8	(*(CAN_MODATAH0_type*) 0xf0005114u)	/* Message Object 8 Data Register High  */
#define CAN_MODATAH9	(*(CAN_MODATAH0_type*) 0xf0005134u)	/* Message Object 9 Data Register High  */

typedef volatile union
{
	struct
	{ 
		unsigned int DB0            : 8;
		unsigned int DB1            : 8;
		unsigned int DB2            : 8;
		unsigned int DB3            : 8;
	} B;
	int I;
	unsigned int U;

} CAN_MODATAL0_type;
#define CAN_MODATAL0	(*(CAN_MODATAL0_type*) 0xf0005010u)	/* Message Object 0 Data Register Low  */
#define CAN_MODATAL1	(*(CAN_MODATAL0_type*) 0xf0005030u)	/* Message Object 1 Data Register Low  */
#define CAN_MODATAL10	(*(CAN_MODATAL0_type*) 0xf0005150u)	/* Message Object 10 Data Register Low  */
#define CAN_MODATAL11	(*(CAN_MODATAL0_type*) 0xf0005170u)	/* Message Object 11 Data Register Low  */
#define CAN_MODATAL12	(*(CAN_MODATAL0_type*) 0xf0005190u)	/* Message Object 12 Data Register Low  */
#define CAN_MODATAL13	(*(CAN_MODATAL0_type*) 0xf00051b0u)	/* Message Object 13 Data Register Low  */
#define CAN_MODATAL14	(*(CAN_MODATAL0_type*) 0xf00051d0u)	/* Message Object 14 Data Register Low  */
#define CAN_MODATAL15	(*(CAN_MODATAL0_type*) 0xf00051f0u)	/* Message Object 15 Data Register Low  */
#define CAN_MODATAL16	(*(CAN_MODATAL0_type*) 0xf0005210u)	/* Message Object 16 Data Register Low  */
#define CAN_MODATAL17	(*(CAN_MODATAL0_type*) 0xf0005230u)	/* Message Object 17 Data Register Low  */
#define CAN_MODATAL18	(*(CAN_MODATAL0_type*) 0xf0005250u)	/* Message Object 18 Data Register Low  */
#define CAN_MODATAL19	(*(CAN_MODATAL0_type*) 0xf0005270u)	/* Message Object 19 Data Register Low  */
#define CAN_MODATAL2	(*(CAN_MODATAL0_type*) 0xf0005050u)	/* Message Object 2 Data Register Low  */
#define CAN_MODATAL20	(*(CAN_MODATAL0_type*) 0xf0005290u)	/* Message Object 20 Data Register Low  */
#define CAN_MODATAL21	(*(CAN_MODATAL0_type*) 0xf00052b0u)	/* Message Object 21 Data Register Low  */
#define CAN_MODATAL22	(*(CAN_MODATAL0_type*) 0xf00052d0u)	/* Message Object 22 Data Register Low  */
#define CAN_MODATAL23	(*(CAN_MODATAL0_type*) 0xf00052f0u)	/* Message Object 23 Data Register Low  */
#define CAN_MODATAL24	(*(CAN_MODATAL0_type*) 0xf0005310u)	/* Message Object 24 Data Register Low  */
#define CAN_MODATAL25	(*(CAN_MODATAL0_type*) 0xf0005330u)	/* Message Object 25 Data Register Low  */
#define CAN_MODATAL26	(*(CAN_MODATAL0_type*) 0xf0005350u)	/* Message Object 26 Data Register Low  */
#define CAN_MODATAL27	(*(CAN_MODATAL0_type*) 0xf0005370u)	/* Message Object 27 Data Register Low  */
#define CAN_MODATAL28	(*(CAN_MODATAL0_type*) 0xf0005390u)	/* Message Object 28 Data Register Low  */
#define CAN_MODATAL29	(*(CAN_MODATAL0_type*) 0xf00053b0u)	/* Message Object 29 Data Register Low  */
#define CAN_MODATAL3	(*(CAN_MODATAL0_type*) 0xf0005070u)	/* Message Object 3 Data Register Low  */
#define CAN_MODATAL30	(*(CAN_MODATAL0_type*) 0xf00053d0u)	/* Message Object 30 Data Register Low  */
#define CAN_MODATAL31	(*(CAN_MODATAL0_type*) 0xf00053f0u)	/* Message Object 31 Data Register Low  */
#define CAN_MODATAL32	(*(CAN_MODATAL0_type*) 0xf0005410u)	/* Message Object 32 Data Register Low  */
#define CAN_MODATAL33	(*(CAN_MODATAL0_type*) 0xf0005430u)	/* Message Object 33 Data Register Low  */
#define CAN_MODATAL34	(*(CAN_MODATAL0_type*) 0xf0005450u)	/* Message Object 34 Data Register Low  */
#define CAN_MODATAL35	(*(CAN_MODATAL0_type*) 0xf0005470u)	/* Message Object 35 Data Register Low  */
#define CAN_MODATAL36	(*(CAN_MODATAL0_type*) 0xf0005490u)	/* Message Object 36 Data Register Low  */
#define CAN_MODATAL37	(*(CAN_MODATAL0_type*) 0xf00054b0u)	/* Message Object 37 Data Register Low  */
#define CAN_MODATAL38	(*(CAN_MODATAL0_type*) 0xf00054d0u)	/* Message Object 38 Data Register Low  */
#define CAN_MODATAL39	(*(CAN_MODATAL0_type*) 0xf00054f0u)	/* Message Object 39 Data Register Low  */
#define CAN_MODATAL4	(*(CAN_MODATAL0_type*) 0xf0005090u)	/* Message Object 4 Data Register Low  */
#define CAN_MODATAL40	(*(CAN_MODATAL0_type*) 0xf0005510u)	/* Message Object 40 Data Register Low  */
#define CAN_MODATAL41	(*(CAN_MODATAL0_type*) 0xf0005530u)	/* Message Object 41 Data Register Low  */
#define CAN_MODATAL42	(*(CAN_MODATAL0_type*) 0xf0005550u)	/* Message Object 42 Data Register Low  */
#define CAN_MODATAL43	(*(CAN_MODATAL0_type*) 0xf0005570u)	/* Message Object 43 Data Register Low  */
#define CAN_MODATAL44	(*(CAN_MODATAL0_type*) 0xf0005590u)	/* Message Object 44 Data Register Low  */
#define CAN_MODATAL45	(*(CAN_MODATAL0_type*) 0xf00055b0u)	/* Message Object 45 Data Register Low  */
#define CAN_MODATAL46	(*(CAN_MODATAL0_type*) 0xf00055d0u)	/* Message Object 46 Data Register Low  */
#define CAN_MODATAL47	(*(CAN_MODATAL0_type*) 0xf00055f0u)	/* Message Object 47 Data Register Low  */
#define CAN_MODATAL48	(*(CAN_MODATAL0_type*) 0xf0005610u)	/* Message Object 48 Data Register Low  */
#define CAN_MODATAL49	(*(CAN_MODATAL0_type*) 0xf0005630u)	/* Message Object 49 Data Register Low  */
#define CAN_MODATAL5	(*(CAN_MODATAL0_type*) 0xf00050b0u)	/* Message Object 5 Data Register Low  */
#define CAN_MODATAL50	(*(CAN_MODATAL0_type*) 0xf0005650u)	/* Message Object 50 Data Register Low  */
#define CAN_MODATAL51	(*(CAN_MODATAL0_type*) 0xf0005670u)	/* Message Object 51 Data Register Low  */
#define CAN_MODATAL52	(*(CAN_MODATAL0_type*) 0xf0005690u)	/* Message Object 52 Data Register Low  */
#define CAN_MODATAL53	(*(CAN_MODATAL0_type*) 0xf00056b0u)	/* Message Object 53 Data Register Low  */
#define CAN_MODATAL54	(*(CAN_MODATAL0_type*) 0xf00056d0u)	/* Message Object 54 Data Register Low  */
#define CAN_MODATAL55	(*(CAN_MODATAL0_type*) 0xf00056f0u)	/* Message Object 55 Data Register Low  */
#define CAN_MODATAL56	(*(CAN_MODATAL0_type*) 0xf0005710u)	/* Message Object 56 Data Register Low  */
#define CAN_MODATAL57	(*(CAN_MODATAL0_type*) 0xf0005730u)	/* Message Object 57 Data Register Low  */
#define CAN_MODATAL58	(*(CAN_MODATAL0_type*) 0xf0005750u)	/* Message Object 58 Data Register Low  */
#define CAN_MODATAL59	(*(CAN_MODATAL0_type*) 0xf0005770u)	/* Message Object 59 Data Register Low  */
#define CAN_MODATAL6	(*(CAN_MODATAL0_type*) 0xf00050d0u)	/* Message Object 6 Data Register Low  */
#define CAN_MODATAL60	(*(CAN_MODATAL0_type*) 0xf0005790u)	/* Message Object 60 Data Register Low  */
#define CAN_MODATAL61	(*(CAN_MODATAL0_type*) 0xf00057b0u)	/* Message Object 61 Data Register Low  */
#define CAN_MODATAL62	(*(CAN_MODATAL0_type*) 0xf00057d0u)	/* Message Object 62 Data Register Low  */
#define CAN_MODATAL63	(*(CAN_MODATAL0_type*) 0xf00057f0u)	/* Message Object 63 Data Register Low  */
#define CAN_MODATAL7	(*(CAN_MODATAL0_type*) 0xf00050f0u)	/* Message Object 7 Data Register Low  */
#define CAN_MODATAL8	(*(CAN_MODATAL0_type*) 0xf0005110u)	/* Message Object 8 Data Register Low  */
#define CAN_MODATAL9	(*(CAN_MODATAL0_type*) 0xf0005130u)	/* Message Object 9 Data Register Low  */

typedef volatile union
{
	struct
	{ 
		unsigned int MMC            : 4;
		unsigned int                : 4;
		unsigned int GDFS           : 1;
		unsigned int IDC            : 1;
		unsigned int DLCC           : 1;
		unsigned int DATC           : 1;
		unsigned int                : 4;
		unsigned int RXIE           : 1;
		unsigned int TXIE           : 1;
		unsigned int OVIE           : 1;
		unsigned int                : 1;
		unsigned int FRREN          : 1;
		unsigned int RMM            : 1;
		unsigned int SDT            : 1;
		unsigned int STT            : 1;
		unsigned int DLC            : 4;
		unsigned int                : 4;
	} B;
	int I;
	unsigned int U;

} CAN_MOFCR0_type;
#define CAN_MOFCR0	(*(CAN_MOFCR0_type*) 0xf0005000u)	/* Message Object 0 Function Control Register  */
#define CAN_MOFCR1	(*(CAN_MOFCR0_type*) 0xf0005020u)	/* Message Object 1 Function Control Register  */
#define CAN_MOFCR10	(*(CAN_MOFCR0_type*) 0xf0005140u)	/* Message Object 10 Function Control Register  */
#define CAN_MOFCR11	(*(CAN_MOFCR0_type*) 0xf0005160u)	/* Message Object 11 Function Control Register  */
#define CAN_MOFCR12	(*(CAN_MOFCR0_type*) 0xf0005180u)	/* Message Object 12 Function Control Register  */
#define CAN_MOFCR13	(*(CAN_MOFCR0_type*) 0xf00051a0u)	/* Message Object 13 Function Control Register  */
#define CAN_MOFCR14	(*(CAN_MOFCR0_type*) 0xf00051c0u)	/* Message Object 14 Function Control Register  */
#define CAN_MOFCR15	(*(CAN_MOFCR0_type*) 0xf00051e0u)	/* Message Object 15 Function Control Register  */
#define CAN_MOFCR16	(*(CAN_MOFCR0_type*) 0xf0005200u)	/* Message Object 16 Function Control Register  */
#define CAN_MOFCR17	(*(CAN_MOFCR0_type*) 0xf0005220u)	/* Message Object 17 Function Control Register  */
#define CAN_MOFCR18	(*(CAN_MOFCR0_type*) 0xf0005240u)	/* Message Object 18 Function Control Register  */
#define CAN_MOFCR19	(*(CAN_MOFCR0_type*) 0xf0005260u)	/* Message Object 19 Function Control Register  */
#define CAN_MOFCR2	(*(CAN_MOFCR0_type*) 0xf0005040u)	/* Message Object 2 Function Control Register  */
#define CAN_MOFCR20	(*(CAN_MOFCR0_type*) 0xf0005280u)	/* Message Object 20 Function Control Register  */
#define CAN_MOFCR21	(*(CAN_MOFCR0_type*) 0xf00052a0u)	/* Message Object 21 Function Control Register  */
#define CAN_MOFCR22	(*(CAN_MOFCR0_type*) 0xf00052c0u)	/* Message Object 22 Function Control Register  */
#define CAN_MOFCR23	(*(CAN_MOFCR0_type*) 0xf00052e0u)	/* Message Object 23 Function Control Register  */
#define CAN_MOFCR24	(*(CAN_MOFCR0_type*) 0xf0005300u)	/* Message Object 24 Function Control Register  */
#define CAN_MOFCR25	(*(CAN_MOFCR0_type*) 0xf0005320u)	/* Message Object 25 Function Control Register  */
#define CAN_MOFCR26	(*(CAN_MOFCR0_type*) 0xf0005340u)	/* Message Object 26 Function Control Register  */
#define CAN_MOFCR27	(*(CAN_MOFCR0_type*) 0xf0005360u)	/* Message Object 27 Function Control Register  */
#define CAN_MOFCR28	(*(CAN_MOFCR0_type*) 0xf0005380u)	/* Message Object 28 Function Control Register  */
#define CAN_MOFCR29	(*(CAN_MOFCR0_type*) 0xf00053a0u)	/* Message Object 29 Function Control Register  */
#define CAN_MOFCR3	(*(CAN_MOFCR0_type*) 0xf0005060u)	/* Message Object 3 Function Control Register  */
#define CAN_MOFCR30	(*(CAN_MOFCR0_type*) 0xf00053c0u)	/* Message Object 30 Function Control Register  */
#define CAN_MOFCR31	(*(CAN_MOFCR0_type*) 0xf00053e0u)	/* Message Object 31 Function Control Register  */
#define CAN_MOFCR32	(*(CAN_MOFCR0_type*) 0xf0005400u)	/* Message Object 32 Function Control Register  */
#define CAN_MOFCR33	(*(CAN_MOFCR0_type*) 0xf0005420u)	/* Message Object 33 Function Control Register  */
#define CAN_MOFCR34	(*(CAN_MOFCR0_type*) 0xf0005440u)	/* Message Object 34 Function Control Register  */
#define CAN_MOFCR35	(*(CAN_MOFCR0_type*) 0xf0005460u)	/* Message Object 35 Function Control Register  */
#define CAN_MOFCR36	(*(CAN_MOFCR0_type*) 0xf0005480u)	/* Message Object 36 Function Control Register  */
#define CAN_MOFCR37	(*(CAN_MOFCR0_type*) 0xf00054a0u)	/* Message Object 37 Function Control Register  */
#define CAN_MOFCR38	(*(CAN_MOFCR0_type*) 0xf00054c0u)	/* Message Object 38 Function Control Register  */
#define CAN_MOFCR39	(*(CAN_MOFCR0_type*) 0xf00054e0u)	/* Message Object 39 Function Control Register  */
#define CAN_MOFCR4	(*(CAN_MOFCR0_type*) 0xf0005080u)	/* Message Object 4 Function Control Register  */
#define CAN_MOFCR40	(*(CAN_MOFCR0_type*) 0xf0005500u)	/* Message Object 40 Function Control Register  */
#define CAN_MOFCR41	(*(CAN_MOFCR0_type*) 0xf0005520u)	/* Message Object 41 Function Control Register  */
#define CAN_MOFCR42	(*(CAN_MOFCR0_type*) 0xf0005540u)	/* Message Object 42 Function Control Register  */
#define CAN_MOFCR43	(*(CAN_MOFCR0_type*) 0xf0005560u)	/* Message Object 43 Function Control Register  */
#define CAN_MOFCR44	(*(CAN_MOFCR0_type*) 0xf0005580u)	/* Message Object 44 Function Control Register  */
#define CAN_MOFCR45	(*(CAN_MOFCR0_type*) 0xf00055a0u)	/* Message Object 45 Function Control Register  */
#define CAN_MOFCR46	(*(CAN_MOFCR0_type*) 0xf00055c0u)	/* Message Object 46 Function Control Register  */
#define CAN_MOFCR47	(*(CAN_MOFCR0_type*) 0xf00055e0u)	/* Message Object 47 Function Control Register  */
#define CAN_MOFCR48	(*(CAN_MOFCR0_type*) 0xf0005600u)	/* Message Object 48 Function Control Register  */
#define CAN_MOFCR49	(*(CAN_MOFCR0_type*) 0xf0005620u)	/* Message Object 49 Function Control Register  */
#define CAN_MOFCR5	(*(CAN_MOFCR0_type*) 0xf00050a0u)	/* Message Object 5 Function Control Register  */
#define CAN_MOFCR50	(*(CAN_MOFCR0_type*) 0xf0005640u)	/* Message Object 50 Function Control Register  */
#define CAN_MOFCR51	(*(CAN_MOFCR0_type*) 0xf0005660u)	/* Message Object 51 Function Control Register  */
#define CAN_MOFCR52	(*(CAN_MOFCR0_type*) 0xf0005680u)	/* Message Object 52 Function Control Register  */
#define CAN_MOFCR53	(*(CAN_MOFCR0_type*) 0xf00056a0u)	/* Message Object 53 Function Control Register  */
#define CAN_MOFCR54	(*(CAN_MOFCR0_type*) 0xf00056c0u)	/* Message Object 54 Function Control Register  */
#define CAN_MOFCR55	(*(CAN_MOFCR0_type*) 0xf00056e0u)	/* Message Object 55 Function Control Register  */
#define CAN_MOFCR56	(*(CAN_MOFCR0_type*) 0xf0005700u)	/* Message Object 56 Function Control Register  */
#define CAN_MOFCR57	(*(CAN_MOFCR0_type*) 0xf0005720u)	/* Message Object 57 Function Control Register  */
#define CAN_MOFCR58	(*(CAN_MOFCR0_type*) 0xf0005740u)	/* Message Object 58 Function Control Register  */
#define CAN_MOFCR59	(*(CAN_MOFCR0_type*) 0xf0005760u)	/* Message Object 59 Function Control Register  */
#define CAN_MOFCR6	(*(CAN_MOFCR0_type*) 0xf00050c0u)	/* Message Object 6 Function Control Register  */
#define CAN_MOFCR60	(*(CAN_MOFCR0_type*) 0xf0005780u)	/* Message Object 60 Function Control Register  */
#define CAN_MOFCR61	(*(CAN_MOFCR0_type*) 0xf00057a0u)	/* Message Object 61 Function Control Register  */
#define CAN_MOFCR62	(*(CAN_MOFCR0_type*) 0xf00057c0u)	/* Message Object 62 Function Control Register  */
#define CAN_MOFCR63	(*(CAN_MOFCR0_type*) 0xf00057e0u)	/* Message Object 63 Function Control Register  */
#define CAN_MOFCR7	(*(CAN_MOFCR0_type*) 0xf00050e0u)	/* Message Object 7 Function Control Register  */
#define CAN_MOFCR8	(*(CAN_MOFCR0_type*) 0xf0005100u)	/* Message Object 8 Function Control Register  */
#define CAN_MOFCR9	(*(CAN_MOFCR0_type*) 0xf0005120u)	/* Message Object 9 Function Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int BOT            : 8;
		unsigned int TOP            : 8;
		unsigned int CUR            : 8;
		unsigned int SEL            : 8;
	} B;
	int I;
	unsigned int U;

} CAN_MOFGPR0_type;
#define CAN_MOFGPR0	(*(CAN_MOFGPR0_type*) 0xf0005004u)	/* Message Object 0 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR1	(*(CAN_MOFGPR0_type*) 0xf0005024u)	/* Message Object 1 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR10	(*(CAN_MOFGPR0_type*) 0xf0005144u)	/* Message Object 10 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR11	(*(CAN_MOFGPR0_type*) 0xf0005164u)	/* Message Object 11 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR12	(*(CAN_MOFGPR0_type*) 0xf0005184u)	/* Message Object 12 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR13	(*(CAN_MOFGPR0_type*) 0xf00051a4u)	/* Message Object 13 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR14	(*(CAN_MOFGPR0_type*) 0xf00051c4u)	/* Message Object 14 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR15	(*(CAN_MOFGPR0_type*) 0xf00051e4u)	/* Message Object 15 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR16	(*(CAN_MOFGPR0_type*) 0xf0005204u)	/* Message Object 16 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR17	(*(CAN_MOFGPR0_type*) 0xf0005224u)	/* Message Object 17 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR18	(*(CAN_MOFGPR0_type*) 0xf0005244u)	/* Message Object 18 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR19	(*(CAN_MOFGPR0_type*) 0xf0005264u)	/* Message Object 19 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR2	(*(CAN_MOFGPR0_type*) 0xf0005044u)	/* Message Object 2 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR20	(*(CAN_MOFGPR0_type*) 0xf0005284u)	/* Message Object 20 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR21	(*(CAN_MOFGPR0_type*) 0xf00052a4u)	/* Message Object 21 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR22	(*(CAN_MOFGPR0_type*) 0xf00052c4u)	/* Message Object 22 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR23	(*(CAN_MOFGPR0_type*) 0xf00052e4u)	/* Message Object 23 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR24	(*(CAN_MOFGPR0_type*) 0xf0005304u)	/* Message Object 24 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR25	(*(CAN_MOFGPR0_type*) 0xf0005324u)	/* Message Object 25 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR26	(*(CAN_MOFGPR0_type*) 0xf0005344u)	/* Message Object 26 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR27	(*(CAN_MOFGPR0_type*) 0xf0005364u)	/* Message Object 27 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR28	(*(CAN_MOFGPR0_type*) 0xf0005384u)	/* Message Object 28 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR29	(*(CAN_MOFGPR0_type*) 0xf00053a4u)	/* Message Object 29 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR3	(*(CAN_MOFGPR0_type*) 0xf0005064u)	/* Message Object 3 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR30	(*(CAN_MOFGPR0_type*) 0xf00053c4u)	/* Message Object 30 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR31	(*(CAN_MOFGPR0_type*) 0xf00053e4u)	/* Message Object 31 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR32	(*(CAN_MOFGPR0_type*) 0xf0005404u)	/* Message Object 32 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR33	(*(CAN_MOFGPR0_type*) 0xf0005424u)	/* Message Object 33 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR34	(*(CAN_MOFGPR0_type*) 0xf0005444u)	/* Message Object 34 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR35	(*(CAN_MOFGPR0_type*) 0xf0005464u)	/* Message Object 35 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR36	(*(CAN_MOFGPR0_type*) 0xf0005484u)	/* Message Object 36 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR37	(*(CAN_MOFGPR0_type*) 0xf00054a4u)	/* Message Object 37 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR38	(*(CAN_MOFGPR0_type*) 0xf00054c4u)	/* Message Object 38 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR39	(*(CAN_MOFGPR0_type*) 0xf00054e4u)	/* Message Object 39 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR4	(*(CAN_MOFGPR0_type*) 0xf0005084u)	/* Message Object 4 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR40	(*(CAN_MOFGPR0_type*) 0xf0005504u)	/* Message Object 40 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR41	(*(CAN_MOFGPR0_type*) 0xf0005524u)	/* Message Object 41 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR42	(*(CAN_MOFGPR0_type*) 0xf0005544u)	/* Message Object 42 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR43	(*(CAN_MOFGPR0_type*) 0xf0005564u)	/* Message Object 43 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR44	(*(CAN_MOFGPR0_type*) 0xf0005584u)	/* Message Object 44 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR45	(*(CAN_MOFGPR0_type*) 0xf00055a4u)	/* Message Object 45 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR46	(*(CAN_MOFGPR0_type*) 0xf00055c4u)	/* Message Object 46 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR47	(*(CAN_MOFGPR0_type*) 0xf00055e4u)	/* Message Object 47 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR48	(*(CAN_MOFGPR0_type*) 0xf0005604u)	/* Message Object 48 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR49	(*(CAN_MOFGPR0_type*) 0xf0005624u)	/* Message Object 49 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR5	(*(CAN_MOFGPR0_type*) 0xf00050a4u)	/* Message Object 5 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR50	(*(CAN_MOFGPR0_type*) 0xf0005644u)	/* Message Object 50 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR51	(*(CAN_MOFGPR0_type*) 0xf0005664u)	/* Message Object 51 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR52	(*(CAN_MOFGPR0_type*) 0xf0005684u)	/* Message Object 52 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR53	(*(CAN_MOFGPR0_type*) 0xf00056a4u)	/* Message Object 53 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR54	(*(CAN_MOFGPR0_type*) 0xf00056c4u)	/* Message Object 54 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR55	(*(CAN_MOFGPR0_type*) 0xf00056e4u)	/* Message Object 55 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR56	(*(CAN_MOFGPR0_type*) 0xf0005704u)	/* Message Object 56 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR57	(*(CAN_MOFGPR0_type*) 0xf0005724u)	/* Message Object 57 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR58	(*(CAN_MOFGPR0_type*) 0xf0005744u)	/* Message Object 58 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR59	(*(CAN_MOFGPR0_type*) 0xf0005764u)	/* Message Object 59 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR6	(*(CAN_MOFGPR0_type*) 0xf00050c4u)	/* Message Object 6 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR60	(*(CAN_MOFGPR0_type*) 0xf0005784u)	/* Message Object 60 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR61	(*(CAN_MOFGPR0_type*) 0xf00057a4u)	/* Message Object 61 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR62	(*(CAN_MOFGPR0_type*) 0xf00057c4u)	/* Message Object 62 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR63	(*(CAN_MOFGPR0_type*) 0xf00057e4u)	/* Message Object 63 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR7	(*(CAN_MOFGPR0_type*) 0xf00050e4u)	/* Message Object 7 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR8	(*(CAN_MOFGPR0_type*) 0xf0005104u)	/* Message Object 8 FIFO/Gateway Pointer Register  */
#define CAN_MOFGPR9	(*(CAN_MOFGPR0_type*) 0xf0005124u)	/* Message Object 9 FIFO/Gateway Pointer Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int RXINP          : 4;
		unsigned int TXINP          : 4;
		unsigned int MPN            : 8;
		unsigned int CFCVAL         : 16;
	} B;
	int I;
	unsigned int U;

} CAN_MOIPR0_type;
#define CAN_MOIPR0	(*(CAN_MOIPR0_type*) 0xf0005008u)	/* Message Object 0 Interrupt Pointer Register  */
#define CAN_MOIPR1	(*(CAN_MOIPR0_type*) 0xf0005028u)	/* Message Object 1 Interrupt Pointer Register  */
#define CAN_MOIPR10	(*(CAN_MOIPR0_type*) 0xf0005148u)	/* Message Object 10 Interrupt Pointer Register  */
#define CAN_MOIPR11	(*(CAN_MOIPR0_type*) 0xf0005168u)	/* Message Object 11 Interrupt Pointer Register  */
#define CAN_MOIPR12	(*(CAN_MOIPR0_type*) 0xf0005188u)	/* Message Object 12 Interrupt Pointer Register  */
#define CAN_MOIPR13	(*(CAN_MOIPR0_type*) 0xf00051a8u)	/* Message Object 13 Interrupt Pointer Register  */
#define CAN_MOIPR14	(*(CAN_MOIPR0_type*) 0xf00051c8u)	/* Message Object 14 Interrupt Pointer Register  */
#define CAN_MOIPR15	(*(CAN_MOIPR0_type*) 0xf00051e8u)	/* Message Object 15 Interrupt Pointer Register  */
#define CAN_MOIPR16	(*(CAN_MOIPR0_type*) 0xf0005208u)	/* Message Object 16 Interrupt Pointer Register  */
#define CAN_MOIPR17	(*(CAN_MOIPR0_type*) 0xf0005228u)	/* Message Object 17 Interrupt Pointer Register  */
#define CAN_MOIPR18	(*(CAN_MOIPR0_type*) 0xf0005248u)	/* Message Object 18 Interrupt Pointer Register  */
#define CAN_MOIPR19	(*(CAN_MOIPR0_type*) 0xf0005268u)	/* Message Object 19 Interrupt Pointer Register  */
#define CAN_MOIPR2	(*(CAN_MOIPR0_type*) 0xf0005048u)	/* Message Object 2 Interrupt Pointer Register  */
#define CAN_MOIPR20	(*(CAN_MOIPR0_type*) 0xf0005288u)	/* Message Object 20 Interrupt Pointer Register  */
#define CAN_MOIPR21	(*(CAN_MOIPR0_type*) 0xf00052a8u)	/* Message Object 21 Interrupt Pointer Register  */
#define CAN_MOIPR22	(*(CAN_MOIPR0_type*) 0xf00052c8u)	/* Message Object 22 Interrupt Pointer Register  */
#define CAN_MOIPR23	(*(CAN_MOIPR0_type*) 0xf00052e8u)	/* Message Object 23 Interrupt Pointer Register  */
#define CAN_MOIPR24	(*(CAN_MOIPR0_type*) 0xf0005308u)	/* Message Object 24 Interrupt Pointer Register  */
#define CAN_MOIPR25	(*(CAN_MOIPR0_type*) 0xf0005328u)	/* Message Object 25 Interrupt Pointer Register  */
#define CAN_MOIPR26	(*(CAN_MOIPR0_type*) 0xf0005348u)	/* Message Object 26 Interrupt Pointer Register  */
#define CAN_MOIPR27	(*(CAN_MOIPR0_type*) 0xf0005368u)	/* Message Object 27 Interrupt Pointer Register  */
#define CAN_MOIPR28	(*(CAN_MOIPR0_type*) 0xf0005388u)	/* Message Object 28 Interrupt Pointer Register  */
#define CAN_MOIPR29	(*(CAN_MOIPR0_type*) 0xf00053a8u)	/* Message Object 29 Interrupt Pointer Register  */
#define CAN_MOIPR3	(*(CAN_MOIPR0_type*) 0xf0005068u)	/* Message Object 3 Interrupt Pointer Register  */
#define CAN_MOIPR30	(*(CAN_MOIPR0_type*) 0xf00053c8u)	/* Message Object 30 Interrupt Pointer Register  */
#define CAN_MOIPR31	(*(CAN_MOIPR0_type*) 0xf00053e8u)	/* Message Object 31 Interrupt Pointer Register  */
#define CAN_MOIPR32	(*(CAN_MOIPR0_type*) 0xf0005408u)	/* Message Object 32 Interrupt Pointer Register  */
#define CAN_MOIPR33	(*(CAN_MOIPR0_type*) 0xf0005428u)	/* Message Object 33 Interrupt Pointer Register  */
#define CAN_MOIPR34	(*(CAN_MOIPR0_type*) 0xf0005448u)	/* Message Object 34 Interrupt Pointer Register  */
#define CAN_MOIPR35	(*(CAN_MOIPR0_type*) 0xf0005468u)	/* Message Object 35 Interrupt Pointer Register  */
#define CAN_MOIPR36	(*(CAN_MOIPR0_type*) 0xf0005488u)	/* Message Object 36 Interrupt Pointer Register  */
#define CAN_MOIPR37	(*(CAN_MOIPR0_type*) 0xf00054a8u)	/* Message Object 37 Interrupt Pointer Register  */
#define CAN_MOIPR38	(*(CAN_MOIPR0_type*) 0xf00054c8u)	/* Message Object 38 Interrupt Pointer Register  */
#define CAN_MOIPR39	(*(CAN_MOIPR0_type*) 0xf00054e8u)	/* Message Object 39 Interrupt Pointer Register  */
#define CAN_MOIPR4	(*(CAN_MOIPR0_type*) 0xf0005088u)	/* Message Object 4 Interrupt Pointer Register  */
#define CAN_MOIPR40	(*(CAN_MOIPR0_type*) 0xf0005508u)	/* Message Object 40 Interrupt Pointer Register  */
#define CAN_MOIPR41	(*(CAN_MOIPR0_type*) 0xf0005528u)	/* Message Object 41 Interrupt Pointer Register  */
#define CAN_MOIPR42	(*(CAN_MOIPR0_type*) 0xf0005548u)	/* Message Object 42 Interrupt Pointer Register  */
#define CAN_MOIPR43	(*(CAN_MOIPR0_type*) 0xf0005568u)	/* Message Object 43 Interrupt Pointer Register  */
#define CAN_MOIPR44	(*(CAN_MOIPR0_type*) 0xf0005588u)	/* Message Object 44 Interrupt Pointer Register  */
#define CAN_MOIPR45	(*(CAN_MOIPR0_type*) 0xf00055a8u)	/* Message Object 45 Interrupt Pointer Register  */
#define CAN_MOIPR46	(*(CAN_MOIPR0_type*) 0xf00055c8u)	/* Message Object 46 Interrupt Pointer Register  */
#define CAN_MOIPR47	(*(CAN_MOIPR0_type*) 0xf00055e8u)	/* Message Object 47 Interrupt Pointer Register  */
#define CAN_MOIPR48	(*(CAN_MOIPR0_type*) 0xf0005608u)	/* Message Object 48 Interrupt Pointer Register  */
#define CAN_MOIPR49	(*(CAN_MOIPR0_type*) 0xf0005628u)	/* Message Object 49 Interrupt Pointer Register  */
#define CAN_MOIPR5	(*(CAN_MOIPR0_type*) 0xf00050a8u)	/* Message Object 5 Interrupt Pointer Register  */
#define CAN_MOIPR50	(*(CAN_MOIPR0_type*) 0xf0005648u)	/* Message Object 50 Interrupt Pointer Register  */
#define CAN_MOIPR51	(*(CAN_MOIPR0_type*) 0xf0005668u)	/* Message Object 51 Interrupt Pointer Register  */
#define CAN_MOIPR52	(*(CAN_MOIPR0_type*) 0xf0005688u)	/* Message Object 52 Interrupt Pointer Register  */
#define CAN_MOIPR53	(*(CAN_MOIPR0_type*) 0xf00056a8u)	/* Message Object 53 Interrupt Pointer Register  */
#define CAN_MOIPR54	(*(CAN_MOIPR0_type*) 0xf00056c8u)	/* Message Object 54 Interrupt Pointer Register  */
#define CAN_MOIPR55	(*(CAN_MOIPR0_type*) 0xf00056e8u)	/* Message Object 55 Interrupt Pointer Register  */
#define CAN_MOIPR56	(*(CAN_MOIPR0_type*) 0xf0005708u)	/* Message Object 56 Interrupt Pointer Register  */
#define CAN_MOIPR57	(*(CAN_MOIPR0_type*) 0xf0005728u)	/* Message Object 57 Interrupt Pointer Register  */
#define CAN_MOIPR58	(*(CAN_MOIPR0_type*) 0xf0005748u)	/* Message Object 58 Interrupt Pointer Register  */
#define CAN_MOIPR59	(*(CAN_MOIPR0_type*) 0xf0005768u)	/* Message Object 59 Interrupt Pointer Register  */
#define CAN_MOIPR6	(*(CAN_MOIPR0_type*) 0xf00050c8u)	/* Message Object 6 Interrupt Pointer Register  */
#define CAN_MOIPR60	(*(CAN_MOIPR0_type*) 0xf0005788u)	/* Message Object 60 Interrupt Pointer Register  */
#define CAN_MOIPR61	(*(CAN_MOIPR0_type*) 0xf00057a8u)	/* Message Object 61 Interrupt Pointer Register  */
#define CAN_MOIPR62	(*(CAN_MOIPR0_type*) 0xf00057c8u)	/* Message Object 62 Interrupt Pointer Register  */
#define CAN_MOIPR63	(*(CAN_MOIPR0_type*) 0xf00057e8u)	/* Message Object 63 Interrupt Pointer Register  */
#define CAN_MOIPR7	(*(CAN_MOIPR0_type*) 0xf00050e8u)	/* Message Object 7 Interrupt Pointer Register  */
#define CAN_MOIPR8	(*(CAN_MOIPR0_type*) 0xf0005108u)	/* Message Object 8 Interrupt Pointer Register  */
#define CAN_MOIPR9	(*(CAN_MOIPR0_type*) 0xf0005128u)	/* Message Object 9 Interrupt Pointer Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RXPND          : 1;
		/* const */ unsigned int TXPND          : 1;
		/* const */ unsigned int RXUPD          : 1;
		/* const */ unsigned int NEWDAT         : 1;
		/* const */ unsigned int MSGLST         : 1;
		/* const */ unsigned int MSGVAL         : 1;
		/* const */ unsigned int RTSEL          : 1;
		/* const */ unsigned int RXEN           : 1;
		/* const */ unsigned int TXRQ           : 1;
		/* const */ unsigned int TXEN0          : 1;
		/* const */ unsigned int TXEN1          : 1;
		/* const */ unsigned int DIR            : 1;
		/* const */ unsigned int LIST           : 4;
		/* const */ unsigned int PPREV          : 8;
		/* const */ unsigned int PNEXT          : 8;
	} B;
	int I;
	unsigned int U;

} CAN_MOSTAT0_type;
#define CAN_MOSTAT0	(*(CAN_MOSTAT0_type*) 0xf000501cu)	/* Message Object 0 Status Register  */
#define CAN_MOSTAT1	(*(CAN_MOSTAT0_type*) 0xf000503cu)	/* Message Object 1 Status Register  */
#define CAN_MOSTAT10	(*(CAN_MOSTAT0_type*) 0xf000515cu)	/* Message Object 10 Status Register  */
#define CAN_MOSTAT11	(*(CAN_MOSTAT0_type*) 0xf000517cu)	/* Message Object 11 Status Register  */
#define CAN_MOSTAT12	(*(CAN_MOSTAT0_type*) 0xf000519cu)	/* Message Object 12 Status Register  */
#define CAN_MOSTAT13	(*(CAN_MOSTAT0_type*) 0xf00051bcu)	/* Message Object 13 Status Register  */
#define CAN_MOSTAT14	(*(CAN_MOSTAT0_type*) 0xf00051dcu)	/* Message Object 14 Status Register  */
#define CAN_MOSTAT15	(*(CAN_MOSTAT0_type*) 0xf00051fcu)	/* Message Object 15 Status Register  */
#define CAN_MOSTAT16	(*(CAN_MOSTAT0_type*) 0xf000521cu)	/* Message Object 16 Status Register  */
#define CAN_MOSTAT17	(*(CAN_MOSTAT0_type*) 0xf000523cu)	/* Message Object 17 Status Register  */
#define CAN_MOSTAT18	(*(CAN_MOSTAT0_type*) 0xf000525cu)	/* Message Object 18 Status Register  */
#define CAN_MOSTAT19	(*(CAN_MOSTAT0_type*) 0xf000527cu)	/* Message Object 19 Status Register  */
#define CAN_MOSTAT2	(*(CAN_MOSTAT0_type*) 0xf000505cu)	/* Message Object 2 Status Register  */
#define CAN_MOSTAT20	(*(CAN_MOSTAT0_type*) 0xf000529cu)	/* Message Object 20 Status Register  */
#define CAN_MOSTAT21	(*(CAN_MOSTAT0_type*) 0xf00052bcu)	/* Message Object 21 Status Register  */
#define CAN_MOSTAT22	(*(CAN_MOSTAT0_type*) 0xf00052dcu)	/* Message Object 22 Status Register  */
#define CAN_MOSTAT23	(*(CAN_MOSTAT0_type*) 0xf00052fcu)	/* Message Object 23 Status Register  */
#define CAN_MOSTAT24	(*(CAN_MOSTAT0_type*) 0xf000531cu)	/* Message Object 24 Status Register  */
#define CAN_MOSTAT25	(*(CAN_MOSTAT0_type*) 0xf000533cu)	/* Message Object 25 Status Register  */
#define CAN_MOSTAT26	(*(CAN_MOSTAT0_type*) 0xf000535cu)	/* Message Object 26 Status Register  */
#define CAN_MOSTAT27	(*(CAN_MOSTAT0_type*) 0xf000537cu)	/* Message Object 27 Status Register  */
#define CAN_MOSTAT28	(*(CAN_MOSTAT0_type*) 0xf000539cu)	/* Message Object 28 Status Register  */
#define CAN_MOSTAT29	(*(CAN_MOSTAT0_type*) 0xf00053bcu)	/* Message Object 29 Status Register  */
#define CAN_MOSTAT3	(*(CAN_MOSTAT0_type*) 0xf000507cu)	/* Message Object 3 Status Register  */
#define CAN_MOSTAT30	(*(CAN_MOSTAT0_type*) 0xf00053dcu)	/* Message Object 30 Status Register  */
#define CAN_MOSTAT31	(*(CAN_MOSTAT0_type*) 0xf00053fcu)	/* Message Object 31 Status Register  */
#define CAN_MOSTAT32	(*(CAN_MOSTAT0_type*) 0xf000541cu)	/* Message Object 32 Status Register  */
#define CAN_MOSTAT33	(*(CAN_MOSTAT0_type*) 0xf000543cu)	/* Message Object 33 Status Register  */
#define CAN_MOSTAT34	(*(CAN_MOSTAT0_type*) 0xf000545cu)	/* Message Object 34 Status Register  */
#define CAN_MOSTAT35	(*(CAN_MOSTAT0_type*) 0xf000547cu)	/* Message Object 35 Status Register  */
#define CAN_MOSTAT36	(*(CAN_MOSTAT0_type*) 0xf000549cu)	/* Message Object 36 Status Register  */
#define CAN_MOSTAT37	(*(CAN_MOSTAT0_type*) 0xf00054bcu)	/* Message Object 37 Status Register  */
#define CAN_MOSTAT38	(*(CAN_MOSTAT0_type*) 0xf00054dcu)	/* Message Object 38 Status Register  */
#define CAN_MOSTAT39	(*(CAN_MOSTAT0_type*) 0xf00054fcu)	/* Message Object 39 Status Register  */
#define CAN_MOSTAT4	(*(CAN_MOSTAT0_type*) 0xf000509cu)	/* Message Object 4 Status Register  */
#define CAN_MOSTAT40	(*(CAN_MOSTAT0_type*) 0xf000551cu)	/* Message Object 40 Status Register  */
#define CAN_MOSTAT41	(*(CAN_MOSTAT0_type*) 0xf000553cu)	/* Message Object 41 Status Register  */
#define CAN_MOSTAT42	(*(CAN_MOSTAT0_type*) 0xf000555cu)	/* Message Object 42 Status Register  */
#define CAN_MOSTAT43	(*(CAN_MOSTAT0_type*) 0xf000557cu)	/* Message Object 43 Status Register  */
#define CAN_MOSTAT44	(*(CAN_MOSTAT0_type*) 0xf000559cu)	/* Message Object 44 Status Register  */
#define CAN_MOSTAT45	(*(CAN_MOSTAT0_type*) 0xf00055bcu)	/* Message Object 45 Status Register  */
#define CAN_MOSTAT46	(*(CAN_MOSTAT0_type*) 0xf00055dcu)	/* Message Object 46 Status Register  */
#define CAN_MOSTAT47	(*(CAN_MOSTAT0_type*) 0xf00055fcu)	/* Message Object 47 Status Register  */
#define CAN_MOSTAT48	(*(CAN_MOSTAT0_type*) 0xf000561cu)	/* Message Object 48 Status Register  */
#define CAN_MOSTAT49	(*(CAN_MOSTAT0_type*) 0xf000563cu)	/* Message Object 49 Status Register  */
#define CAN_MOSTAT5	(*(CAN_MOSTAT0_type*) 0xf00050bcu)	/* Message Object 5 Status Register  */
#define CAN_MOSTAT50	(*(CAN_MOSTAT0_type*) 0xf000565cu)	/* Message Object 50 Status Register  */
#define CAN_MOSTAT51	(*(CAN_MOSTAT0_type*) 0xf000567cu)	/* Message Object 51 Status Register  */
#define CAN_MOSTAT52	(*(CAN_MOSTAT0_type*) 0xf000569cu)	/* Message Object 52 Status Register  */
#define CAN_MOSTAT53	(*(CAN_MOSTAT0_type*) 0xf00056bcu)	/* Message Object 53 Status Register  */
#define CAN_MOSTAT54	(*(CAN_MOSTAT0_type*) 0xf00056dcu)	/* Message Object 54 Status Register  */
#define CAN_MOSTAT55	(*(CAN_MOSTAT0_type*) 0xf00056fcu)	/* Message Object 55 Status Register  */
#define CAN_MOSTAT56	(*(CAN_MOSTAT0_type*) 0xf000571cu)	/* Message Object 56 Status Register  */
#define CAN_MOSTAT57	(*(CAN_MOSTAT0_type*) 0xf000573cu)	/* Message Object 57 Status Register  */
#define CAN_MOSTAT58	(*(CAN_MOSTAT0_type*) 0xf000575cu)	/* Message Object 58 Status Register  */
#define CAN_MOSTAT59	(*(CAN_MOSTAT0_type*) 0xf000577cu)	/* Message Object 59 Status Register  */
#define CAN_MOSTAT6	(*(CAN_MOSTAT0_type*) 0xf00050dcu)	/* Message Object 6 Status Register  */
#define CAN_MOSTAT60	(*(CAN_MOSTAT0_type*) 0xf000579cu)	/* Message Object 60 Status Register  */
#define CAN_MOSTAT61	(*(CAN_MOSTAT0_type*) 0xf00057bcu)	/* Message Object 61 Status Register  */
#define CAN_MOSTAT62	(*(CAN_MOSTAT0_type*) 0xf00057dcu)	/* Message Object 62 Status Register  */
#define CAN_MOSTAT63	(*(CAN_MOSTAT0_type*) 0xf00057fcu)	/* Message Object 63 Status Register  */
#define CAN_MOSTAT7	(*(CAN_MOSTAT0_type*) 0xf00050fcu)	/* Message Object 7 Status Register  */
#define CAN_MOSTAT8	(*(CAN_MOSTAT0_type*) 0xf000511cu)	/* Message Object 8 Status Register  */
#define CAN_MOSTAT9	(*(CAN_MOSTAT0_type*) 0xf000513cu)	/* Message Object 9 Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int INDEX          : 6;
		/* const */ unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} CAN_MSID0_type;
#define CAN_MSID0	(*(CAN_MSID0_type*) 0xf0004180u)	/* Message Index Register 0  */
#define CAN_MSID1	(*(CAN_MSID0_type*) 0xf0004184u)	/* Message Index Register 1  */
#define CAN_MSID2	(*(CAN_MSID0_type*) 0xf0004188u)	/* Message Index Register 2  */
#define CAN_MSID3	(*(CAN_MSID0_type*) 0xf000418cu)	/* Message Index Register 3  */
#define CAN_MSID4	(*(CAN_MSID0_type*) 0xf0004190u)	/* Message Index Register 4  */
#define CAN_MSID5	(*(CAN_MSID0_type*) 0xf0004194u)	/* Message Index Register 5  */
#define CAN_MSID6	(*(CAN_MSID0_type*) 0xf0004198u)	/* Message Index Register 6  */
#define CAN_MSID7	(*(CAN_MSID0_type*) 0xf000419cu)	/* Message Index Register 7  */

typedef volatile union
{
	struct
	{ 
		unsigned int IM             : 32;
	} B;
	int I;
	unsigned int U;

} CAN_MSIMASK_type;
#define CAN_MSIMASK	(*(CAN_MSIMASK_type*) 0xf00041c0u)	/* Message Index Mask Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PND            : 32;
	} B;
	int I;
	unsigned int U;

} CAN_MSPND0_type;
#define CAN_MSPND0	(*(CAN_MSPND0_type*) 0xf0004140u)	/* Message Pending Register 0  */
#define CAN_MSPND1	(*(CAN_MSPND0_type*) 0xf0004144u)	/* Message Pending Register 1  */
#define CAN_MSPND2	(*(CAN_MSPND0_type*) 0xf0004148u)	/* Message Pending Register 2  */
#define CAN_MSPND3	(*(CAN_MSPND0_type*) 0xf000414cu)	/* Message Pending Register 3  */
#define CAN_MSPND4	(*(CAN_MSPND0_type*) 0xf0004150u)	/* Message Pending Register 4  */
#define CAN_MSPND5	(*(CAN_MSPND0_type*) 0xf0004154u)	/* Message Pending Register 5  */
#define CAN_MSPND6	(*(CAN_MSPND0_type*) 0xf0004158u)	/* Message Pending Register 6  */
#define CAN_MSPND7	(*(CAN_MSPND0_type*) 0xf000415cu)	/* Message Pending Register 7  */

typedef volatile union
{
	struct
	{ 
		unsigned int BRP            : 6;
		unsigned int SJW            : 2;
		unsigned int TSEG1          : 4;
		unsigned int TSEG2          : 3;
		unsigned int DIV8           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} CAN_NBTR0_type;
#define CAN_NBTR0	(*(CAN_NBTR0_type*) 0xf0004210u)	/* Node 0 Bit Timing Register  */
#define CAN_NBTR1	(*(CAN_NBTR0_type*) 0xf0004310u)	/* Node 1 Bit Timing Register  */
#define CAN_NBTR2	(*(CAN_NBTR0_type*) 0xf0004410u)	/* Node 2 Bit Timing Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int INIT           : 1;
		unsigned int TRIE           : 1;
		unsigned int LECIE          : 1;
		unsigned int ALIE           : 1;
		unsigned int CANDIS         : 1;
		unsigned int                : 1;
		unsigned int CCE            : 1;
		unsigned int CALM           : 1;
		unsigned int SUSEN          : 1;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} CAN_NCR0_type;
#define CAN_NCR0	(*(CAN_NCR0_type*) 0xf0004200u)	/* Node 0 Control Register  */
#define CAN_NCR1	(*(CAN_NCR0_type*) 0xf0004300u)	/* Node 1 Control Register  */
#define CAN_NCR2	(*(CAN_NCR0_type*) 0xf0004400u)	/* Node 2 Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int REC            : 8;
		unsigned int TEC            : 8;
		unsigned int EWRNLVL        : 8;
		/* const */ unsigned int LETD           : 1;
		/* const */ unsigned int LEINC          : 1;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} CAN_NECNT0_type;
#define CAN_NECNT0	(*(CAN_NECNT0_type*) 0xf0004214u)	/* Node 0 Error Counter Register  */
#define CAN_NECNT1	(*(CAN_NECNT0_type*) 0xf0004314u)	/* Node 1 Error Counter Register  */
#define CAN_NECNT2	(*(CAN_NECNT0_type*) 0xf0004414u)	/* Node 2 Error Counter Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CFC            : 16;
		unsigned int CFSEL          : 3;
		unsigned int CFMOD          : 2;
		unsigned int                : 1;
		unsigned int CFCIE          : 1;
		unsigned int CFCOV          : 1;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} CAN_NFCR0_type;
#define CAN_NFCR0	(*(CAN_NFCR0_type*) 0xf0004218u)	/* Node 0 Frame Counter Register  */
#define CAN_NFCR1	(*(CAN_NFCR0_type*) 0xf0004318u)	/* Node 1 Frame Counter Register  */
#define CAN_NFCR2	(*(CAN_NFCR0_type*) 0xf0004418u)	/* Node 2 Frame Counter Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ALINP          : 4;
		unsigned int LECINP         : 4;
		unsigned int TRINP          : 4;
		unsigned int CFCINP         : 4;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} CAN_NIPR0_type;
#define CAN_NIPR0	(*(CAN_NIPR0_type*) 0xf0004208u)	/* Node 0 Interrupt Pointer Register  */
#define CAN_NIPR1	(*(CAN_NIPR0_type*) 0xf0004308u)	/* Node 1 Interrupt Pointer Register  */
#define CAN_NIPR2	(*(CAN_NIPR0_type*) 0xf0004408u)	/* Node 2 Interrupt Pointer Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int RXSEL          : 3;
		unsigned int                : 5;
		unsigned int LBM            : 1;
		unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} CAN_NPCR0_type;
#define CAN_NPCR0	(*(CAN_NPCR0_type*) 0xf000420cu)	/* Node 0 Port Control Register  */
#define CAN_NPCR1	(*(CAN_NPCR0_type*) 0xf000430cu)	/* Node 1 Port Control Register  */
#define CAN_NPCR2	(*(CAN_NPCR0_type*) 0xf000440cu)	/* Node 2 Port Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int LEC            : 3;
		unsigned int TXOK           : 1;
		unsigned int RXOK           : 1;
		unsigned int ALERT          : 1;
		/* const */ unsigned int EWRN           : 1;
		/* const */ unsigned int BOFF           : 1;
		unsigned int LLE            : 1;
		unsigned int LOE            : 1;
		/* const */ unsigned int SUSACK         : 1;
		unsigned int                : 21;
	} B;
	int I;
	unsigned int U;

} CAN_NSR0_type;
#define CAN_NSR0	(*(CAN_NSR0_type*) 0xf0004204u)	/* Node 0 Status Register  */
#define CAN_NSR1	(*(CAN_NSR0_type*) 0xf0004304u)	/* Node 1 Status Register  */
#define CAN_NSR2	(*(CAN_NSR0_type*) 0xf0004404u)	/* Node 2 Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PANCMD         : 8;
		/* const */ unsigned int BUSY           : 1;
		/* const */ unsigned int RBUSY          : 1;
		unsigned int                : 6;
		unsigned int PANAR1         : 8;
		unsigned int PANAR2         : 8;
	} B;
	int I;
	unsigned int U;

} CAN_PANCTR_type;
#define CAN_PANCTR	(*(CAN_PANCTR_type*) 0xf00041c4u)	/* Panel Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} CAN_SRC0_type;
#define CAN_SRC0	(*(CAN_SRC0_type*) 0xf00040fcu)	/* CAN Service Request Control Register 0  */
#define CAN_SRC1	(*(CAN_SRC0_type*) 0xf00040f8u)	/* CAN Service Request Control Register 1  */
#define CAN_SRC10	(*(CAN_SRC0_type*) 0xf00040d4u)	/* CAN Service Request Control Register 10  */
#define CAN_SRC11	(*(CAN_SRC0_type*) 0xf00040d0u)	/* CAN Service Request Control Register 11  */
#define CAN_SRC12	(*(CAN_SRC0_type*) 0xf00040ccu)	/* CAN Service Request Control Register 12  */
#define CAN_SRC13	(*(CAN_SRC0_type*) 0xf00040c8u)	/* CAN Service Request Control Register 13  */
#define CAN_SRC14	(*(CAN_SRC0_type*) 0xf00040c4u)	/* CAN Service Request Control Register 14  */
#define CAN_SRC15	(*(CAN_SRC0_type*) 0xf00040c0u)	/* CAN Service Request Control Register 15  */
#define CAN_SRC2	(*(CAN_SRC0_type*) 0xf00040f4u)	/* CAN Service Request Control Register 2  */
#define CAN_SRC3	(*(CAN_SRC0_type*) 0xf00040f0u)	/* CAN Service Request Control Register 3  */
#define CAN_SRC4	(*(CAN_SRC0_type*) 0xf00040ecu)	/* CAN Service Request Control Register 4  */
#define CAN_SRC5	(*(CAN_SRC0_type*) 0xf00040e8u)	/* CAN Service Request Control Register 5  */
#define CAN_SRC6	(*(CAN_SRC0_type*) 0xf00040e4u)	/* CAN Service Request Control Register 6  */
#define CAN_SRC7	(*(CAN_SRC0_type*) 0xf00040e0u)	/* CAN Service Request Control Register 7  */
#define CAN_SRC8	(*(CAN_SRC0_type*) 0xf00040dcu)	/* CAN Service Request Control Register 8  */
#define CAN_SRC9	(*(CAN_SRC0_type*) 0xf00040d8u)	/* CAN Service Request Control Register 9  */


/* MLI */
typedef volatile union
{
	struct
	{ 
		unsigned int AEN0           : 1;
		unsigned int AEN1           : 1;
		unsigned int AEN2           : 1;
		unsigned int AEN3           : 1;
		unsigned int AEN4           : 1;
		unsigned int AEN5           : 1;
		unsigned int AEN6           : 1;
		unsigned int AEN7           : 1;
		unsigned int AEN8           : 1;
		unsigned int AEN9           : 1;
		unsigned int AEN10          : 1;
		unsigned int AEN11          : 1;
		unsigned int AEN12          : 1;
		unsigned int AEN13          : 1;
		unsigned int AEN14          : 1;
		unsigned int AEN15          : 1;
		unsigned int AEN16          : 1;
		unsigned int AEN17          : 1;
		unsigned int AEN18          : 1;
		unsigned int AEN19          : 1;
		unsigned int AEN20          : 1;
		unsigned int AEN21          : 1;
		unsigned int AEN22          : 1;
		unsigned int AEN23          : 1;
		unsigned int AEN24          : 1;
		unsigned int AEN25          : 1;
		unsigned int AEN26          : 1;
		unsigned int AEN27          : 1;
		unsigned int AEN28          : 1;
		unsigned int AEN29          : 1;
		unsigned int AEN30          : 1;
		unsigned int AEN31          : 1;
	} B;
	int I;
	unsigned int U;

} MLI0_AER_type;
#define MLI0_AER	(*(MLI0_AER_type*) 0xf010c0b8u)	/* Access Enable Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SLICE0         : 5;
		unsigned int SIZE0          : 3;
		unsigned int SLICE1         : 5;
		unsigned int SIZE1          : 3;
		unsigned int SLICE2         : 5;
		unsigned int SIZE2          : 3;
		unsigned int SLICE3         : 5;
		unsigned int SIZE3          : 3;
	} B;
	int I;
	unsigned int U;

} MLI0_ARR_type;
#define MLI0_ARR	(*(MLI0_ARR_type*) 0xf010c0bcu)	/* Access Range Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STEP           : 10;
		unsigned int                : 1;
		unsigned int SM             : 1;
		unsigned int SC             : 2;
		unsigned int DM             : 2;
		/* const */ unsigned int RESULT         : 10;
		unsigned int                : 2;
		/* const */ unsigned int SUSACK         : 1;
		/* const */ unsigned int SUSREQ         : 1;
		unsigned int ENHW           : 1;
		unsigned int DISCLK         : 1;
	} B;
	int I;
	unsigned int U;

} MLI0_FDR_type;
#define MLI0_FDR	(*(MLI0_FDR_type*) 0xf010c00cu)	/* Fractional Divider Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SIMLI0         : 1;
		unsigned int SIMLI1         : 1;
		unsigned int SIMLI2         : 1;
		unsigned int SIMLI3         : 1;
		unsigned int SIMLI4         : 1;
		unsigned int SIMLI5         : 1;
		unsigned int SIMLI6         : 1;
		unsigned int SIMLI7         : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} MLI0_GINTR_type;
#define MLI0_GINTR	(*(MLI0_GINTR_type*) 0xf010c0b0u)	/* Global Interrupt Set Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MOD_REV        : 8;
		/* const */ unsigned int MOD_TYPE       : 8;
		/* const */ unsigned int MOD_NUMBER     : 16;
	} B;
	int I;
	unsigned int U;

} MLI0_ID_type;
#define MLI0_ID	(*(MLI0_ID_type*) 0xf010c008u)	/* Module Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int TVEA           : 1;
		unsigned int TVEB           : 1;
		unsigned int TVEC           : 1;
		unsigned int TVED           : 1;
		unsigned int TVPA           : 1;
		unsigned int TVPB           : 1;
		unsigned int TVPC           : 1;
		unsigned int TVPD           : 1;
		unsigned int TRS            : 2;
		unsigned int TRP            : 1;
		unsigned int TRE            : 1;
		unsigned int TCE            : 1;
		unsigned int TCP            : 1;
		unsigned int TDP            : 1;
		unsigned int RVE            : 1;
		unsigned int RRS            : 2;
		unsigned int RRPA           : 1;
		unsigned int RRPB           : 1;
		unsigned int RRPC           : 1;
		unsigned int RRPD           : 1;
		unsigned int RVS            : 2;
		unsigned int RVP            : 1;
		unsigned int RCS            : 2;
		unsigned int RCP            : 1;
		unsigned int RCE            : 1;
		unsigned int RDS            : 2;
		unsigned int RDP            : 1;
	} B;
	int I;
	unsigned int U;

} MLI0_OICR_type;
#define MLI0_OICR	(*(MLI0_OICR_type*) 0xf010c0b4u)	/* Output Input Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int ADDR           : 32;
	} B;
	int I;
	unsigned int U;

} MLI0_RADRR_type;
#define MLI0_RADRR	(*(MLI0_RADRR_type*) 0xf010c08cu)	/* Receiver Address Register  */
#define MLI0_RP0BAR	(*(MLI0_RADRR_type*) 0xf010c06cu)	/* Receiver Pipe 0 Base Address Register  */
#define MLI0_RP1BAR	(*(MLI0_RADRR_type*) 0xf010c070u)	/* Receiver Pipe 1 Base Address Register  */
#define MLI0_RP2BAR	(*(MLI0_RADRR_type*) 0xf010c074u)	/* Receiver Pipe 2 Base Address Register  */
#define MLI0_RP3BAR	(*(MLI0_RADRR_type*) 0xf010c078u)	/* Receiver Pipe 3 Base Address Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int DPE            : 4;
		/* const */ unsigned int CMDP3          : 4;
		/* const */ unsigned int MOD            : 1;
		/* const */ unsigned int DW             : 2;
		/* const */ unsigned int TF             : 2;
		/* const */ unsigned int PE             : 1;
		/* const */ unsigned int RPN            : 2;
		unsigned int MPE            : 4;
		unsigned int BEN            : 1;
		unsigned int                : 3;
		unsigned int RCVRST         : 1;
		unsigned int                : 7;
	} B;
	int I;
	unsigned int U;

} MLI0_RCR_type;
#define MLI0_RCR	(*(MLI0_RCR_type*) 0xf010c068u)	/* Receiver Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int DATA           : 32;
	} B;
	int I;
	unsigned int U;

} MLI0_RDATAR_type;
#define MLI0_RDATAR	(*(MLI0_RDATAR_type*) 0xf010c090u)	/* Receiver Data Register  */
#define MLI0_TP0DATAR	(*(MLI0_RDATAR_type*) 0xf010c040u)	/* Transmitter Pipe 0 Data Register  */
#define MLI0_TP1DATAR	(*(MLI0_RDATAR_type*) 0xf010c044u)	/* Transmitter Pipe 1 Data Register  */
#define MLI0_TP2DATAR	(*(MLI0_RDATAR_type*) 0xf010c048u)	/* Transmitter Pipe 2 Data Register  */
#define MLI0_TP3DATAR	(*(MLI0_RDATAR_type*) 0xf010c04cu)	/* Transmitter Pipe 3 Data Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int NFRIE          : 2;
		unsigned int CFRIE0         : 1;
		unsigned int CFRIE1         : 1;
		unsigned int CFRIE2         : 1;
		unsigned int CFRIE3         : 1;
		unsigned int ICE            : 1;
		unsigned int PEIE           : 1;
		unsigned int MPEIE          : 1;
		unsigned int DRAIE          : 1;
		unsigned int                : 6;
		unsigned int NFRIR          : 1;
		unsigned int MEIR           : 1;
		unsigned int CFRIR0         : 1;
		unsigned int CFRIR1         : 1;
		unsigned int CFRIR2         : 1;
		unsigned int CFRIR3         : 1;
		unsigned int ICER           : 1;
		unsigned int PEIR           : 1;
		unsigned int MPEIR          : 1;
		unsigned int DRAIR          : 1;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} MLI0_RIER_type;
#define MLI0_RIER	(*(MLI0_RIER_type*) 0xf010c0a4u)	/* Receiver Interrupt Enable Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int NFRIP          : 3;
		unsigned int                : 1;
		unsigned int CFRIP          : 3;
		unsigned int                : 1;
		unsigned int MPPEIP         : 3;
		unsigned int                : 1;
		unsigned int DRAIP          : 3;
		unsigned int                : 17;
	} B;
	int I;
	unsigned int U;

} MLI0_RINPR_type;
#define MLI0_RINPR	(*(MLI0_RINPR_type*) 0xf010c0acu)	/* Receiver Interrupt Node Pointer Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int NFRI           : 1;
		/* const */ unsigned int MEI            : 1;
		/* const */ unsigned int CFRI0          : 1;
		/* const */ unsigned int CFRI1          : 1;
		/* const */ unsigned int CFRI2          : 1;
		/* const */ unsigned int CFRI3          : 1;
		/* const */ unsigned int IC             : 1;
		/* const */ unsigned int PEI            : 1;
		/* const */ unsigned int MPEI           : 1;
		/* const */ unsigned int DRAI           : 1;
		/* const */ unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} MLI0_RISR_type;
#define MLI0_RISR	(*(MLI0_RISR_type*) 0xf010c0a8u)	/* Receiver Interrupt Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int BS             : 4;
		/* const */ unsigned int                : 2;
		/* const */ unsigned int AP             : 10;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} MLI0_RP0STATR_type;
#define MLI0_RP0STATR	(*(MLI0_RP0STATR_type*) 0xf010c07cu)	/* Receiver Pipe 0 Status Register  */
#define MLI0_RP1STATR	(*(MLI0_RP0STATR_type*) 0xf010c080u)	/* Receiver Pipe 1 Status Register  */
#define MLI0_RP2STATR	(*(MLI0_RP0STATR_type*) 0xf010c084u)	/* Receiver Pipe 2 Status Register  */
#define MLI0_RP3STATR	(*(MLI0_RP0STATR_type*) 0xf010c088u)	/* Receiver Pipe 3 Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SCV0           : 1;
		unsigned int SCV1           : 1;
		unsigned int SCV2           : 1;
		unsigned int SCV3           : 1;
		unsigned int SMOD           : 1;
		unsigned int                : 3;
		unsigned int CDV0           : 1;
		unsigned int CDV1           : 1;
		unsigned int CDV2           : 1;
		unsigned int CDV3           : 1;
		unsigned int CCV0           : 1;
		unsigned int CCV1           : 1;
		unsigned int CCV2           : 1;
		unsigned int CCV3           : 1;
		unsigned int CMOD           : 1;
		unsigned int CBAV           : 1;
		unsigned int                : 6;
		unsigned int CAV            : 1;
		unsigned int CRPE           : 1;
		unsigned int CTPE           : 1;
		unsigned int CNAE           : 1;
		unsigned int CCIV0          : 1;
		unsigned int CCIV1          : 1;
		unsigned int CCIV2          : 1;
		unsigned int CCIV3          : 1;
	} B;
	int I;
	unsigned int U;

} MLI0_SCR_type;
#define MLI0_SCR	(*(MLI0_SCR_type*) 0xf010c094u)	/* Set Clear Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int                : 4;
		/* const */ unsigned int ADDR           : 28;
	} B;
	int I;
	unsigned int U;

} MLI0_TCBAR_type;
#define MLI0_TCBAR	(*(MLI0_TCBAR_type*) 0xf010c064u)	/* Transmitter Copy Base Address Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CMDP0          : 4;
		unsigned int                : 4;
		unsigned int CMDP1          : 4;
		unsigned int                : 4;
		unsigned int CMDP2          : 4;
		unsigned int                : 4;
		unsigned int CMDP3          : 4;
		unsigned int                : 4;
	} B;
	int I;
	unsigned int U;

} MLI0_TCMDR_type;
#define MLI0_TCMDR	(*(MLI0_TCMDR_type*) 0xf010c028u)	/* Transmitter Command Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MOD            : 1;
		unsigned int DNT            : 1;
		unsigned int                : 2;
		unsigned int MPE            : 4;
		unsigned int MNAE           : 2;
		unsigned int MDP            : 4;
		unsigned int NO             : 1;
		unsigned int TP             : 1;
		unsigned int TDEL           : 4;
		unsigned int                : 12;
	} B;
	int I;
	unsigned int U;

} MLI0_TCR_type;
#define MLI0_TCR	(*(MLI0_TCR_type*) 0xf010c010u)	/* Transmitter Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DATA           : 32;
	} B;
	int I;
	unsigned int U;

} MLI0_TDRAR_type;
#define MLI0_TDRAR	(*(MLI0_TDRAR_type*) 0xf010c050u)	/* Transmitter Data Read Answer Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int NFSIE0         : 1;
		unsigned int NFSIE1         : 1;
		unsigned int NFSIE2         : 1;
		unsigned int NFSIE3         : 1;
		unsigned int CFSIE0         : 1;
		unsigned int CFSIE1         : 1;
		unsigned int CFSIE2         : 1;
		unsigned int CFSIE3         : 1;
		unsigned int PEIE           : 1;
		unsigned int TEIE           : 1;
		unsigned int                : 6;
		unsigned int NFSIR0         : 1;
		unsigned int NFSIR1         : 1;
		unsigned int NFSIR2         : 1;
		unsigned int NFSIR3         : 1;
		unsigned int CFSIR0         : 1;
		unsigned int CFSIR1         : 1;
		unsigned int CFSIR2         : 1;
		unsigned int CFSIR3         : 1;
		unsigned int PEIR           : 1;
		unsigned int TEIR           : 1;
		unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} MLI0_TIER_type;
#define MLI0_TIER	(*(MLI0_TIER_type*) 0xf010c098u)	/* Transmitter Interrupt Enable Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int NFSIP0         : 3;
		unsigned int                : 1;
		unsigned int NFSIP1         : 3;
		unsigned int                : 1;
		unsigned int NFSIP2         : 3;
		unsigned int                : 1;
		unsigned int NFSIP3         : 3;
		unsigned int                : 1;
		unsigned int CFSIP          : 3;
		unsigned int                : 1;
		unsigned int PTEIP          : 3;
		unsigned int                : 9;
	} B;
	int I;
	unsigned int U;

} MLI0_TINPR_type;
#define MLI0_TINPR	(*(MLI0_TINPR_type*) 0xf010c0a0u)	/* Transmitter Interrupt Node Pointer Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int NFSI0          : 1;
		/* const */ unsigned int NFSI1          : 1;
		/* const */ unsigned int NFSI2          : 1;
		/* const */ unsigned int NFSI3          : 1;
		/* const */ unsigned int CFSI0          : 1;
		/* const */ unsigned int CFSI1          : 1;
		/* const */ unsigned int CFSI2          : 1;
		/* const */ unsigned int CFSI3          : 1;
		/* const */ unsigned int PEI            : 1;
		/* const */ unsigned int TEI            : 1;
		/* const */ unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} MLI0_TISR_type;
#define MLI0_TISR	(*(MLI0_TISR_type*) 0xf010c09cu)	/* Transmitter Interrupt Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int AOFF           : 16;
		/* const */ unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} MLI0_TP0AOFR_type;
#define MLI0_TP0AOFR	(*(MLI0_TP0AOFR_type*) 0xf010c030u)	/* Transmitter Pipe 0 Address Offset Register  */
#define MLI0_TP1AOFR	(*(MLI0_TP0AOFR_type*) 0xf010c034u)	/* Transmitter Pipe 1 Address Offset Register  */
#define MLI0_TP2AOFR	(*(MLI0_TP0AOFR_type*) 0xf010c038u)	/* Transmitter Pipe 2 Address Offset Register  */
#define MLI0_TP3AOFR	(*(MLI0_TP0AOFR_type*) 0xf010c03cu)	/* Transmitter Pipe 3 Address Offset Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int BS             : 4;
		unsigned int ADDR           : 28;
	} B;
	int I;
	unsigned int U;

} MLI0_TP0BAR_type;
#define MLI0_TP0BAR	(*(MLI0_TP0BAR_type*) 0xf010c054u)	/* Transmitter Pipe 0 Base Address Register  */
#define MLI0_TP1BAR	(*(MLI0_TP0BAR_type*) 0xf010c058u)	/* Transmitter Pipe 1 Base Address Register  */
#define MLI0_TP2BAR	(*(MLI0_TP0BAR_type*) 0xf010c05cu)	/* Transmitter Pipe 2 Base Address Register  */
#define MLI0_TP3BAR	(*(MLI0_TP0BAR_type*) 0xf010c060u)	/* Transmitter Pipe 3 Base Address Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int BS             : 4;
		/* const */ unsigned int DW             : 2;
		/* const */ unsigned int AP             : 10;
		/* const */ unsigned int OP             : 1;
		/* const */ unsigned int                : 15;
	} B;
	int I;
	unsigned int U;

} MLI0_TP0STATR_type;
#define MLI0_TP0STATR	(*(MLI0_TP0STATR_type*) 0xf010c018u)	/* Transmitter Pipe 0 Status Register  */
#define MLI0_TP1STATR	(*(MLI0_TP0STATR_type*) 0xf010c01cu)	/* Transmitter Pipe 1 Status Register  */
#define MLI0_TP2STATR	(*(MLI0_TP0STATR_type*) 0xf010c020u)	/* Transmitter Pipe 2 Status Register  */
#define MLI0_TP3STATR	(*(MLI0_TP0STATR_type*) 0xf010c024u)	/* Transmitter Pipe 3 Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int CIV0           : 1;
		/* const */ unsigned int CIV1           : 1;
		/* const */ unsigned int CIV2           : 1;
		/* const */ unsigned int CIV3           : 1;
		/* const */ unsigned int CV0            : 1;
		/* const */ unsigned int CV1            : 1;
		/* const */ unsigned int CV2            : 1;
		/* const */ unsigned int CV3            : 1;
		/* const */ unsigned int AV             : 1;
		/* const */ unsigned int BAV            : 1;
		/* const */ unsigned int                : 6;
		/* const */ unsigned int DV0            : 1;
		/* const */ unsigned int DV1            : 1;
		/* const */ unsigned int DV2            : 1;
		/* const */ unsigned int DV3            : 1;
		/* const */ unsigned int RP0            : 1;
		/* const */ unsigned int RP1            : 1;
		/* const */ unsigned int RP2            : 1;
		/* const */ unsigned int RP3            : 1;
		/* const */ unsigned int PN             : 2;
		/* const */ unsigned int                : 6;
	} B;
	int I;
	unsigned int U;

} MLI0_TRSTATR_type;
#define MLI0_TRSTATR	(*(MLI0_TRSTATR_type*) 0xf010c02cu)	/* Transmitter Receiver Status Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RDC            : 5;
		/* const */ unsigned int APN            : 2;
		/* const */ unsigned int PE             : 1;
		/* const */ unsigned int NAE            : 1;
		/* const */ unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} MLI0_TSTATR_type;
#define MLI0_TSTATR	(*(MLI0_TSTATR_type*) 0xf010c014u)	/* Transmitter Status Register  */


/* GPTA */
typedef volatile union
{
	struct
	{ 
		unsigned int DFA02          : 4;
		unsigned int DFA04          : 4;
		unsigned int DFA06          : 4;
		unsigned int DFA07          : 4;
		unsigned int DFA03          : 2;
		unsigned int DFALTC         : 3;
		unsigned int                : 11;
	} B;
	int I;
	unsigned int U;

} GPTA0_CKBCTR_type;
#define GPTA0_CKBCTR	(*(GPTA0_CKBCTR_type*) 0xf00018d8u)	/* GPTA0 Clock Bus Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} GPTA0_CLC_type;
#define GPTA0_CLC	(*(GPTA0_CLC_type*) 0xf0001800u)	/* GPTA Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CLKCNT         : 16;
		unsigned int                : 15;
		unsigned int DBGCEN         : 1;
	} B;
	int I;
	unsigned int U;

} GPTA0_DBGCTR_type;
#define GPTA0_DBGCTR	(*(GPTA0_DBGCTR_type*) 0xf0001804u)	/* GPTA Debug Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CAV            : 24;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} GPTA0_DCMCAV0_type;
#define GPTA0_DCMCAV0	(*(GPTA0_DCMCAV0_type*) 0xf0001888u)	/* GPTA0 Duty Cycle Measurement Capture Register 0  */
#define GPTA0_DCMCAV1	(*(GPTA0_DCMCAV0_type*) 0xf0001898u)	/* GPTA0 Duty Cycle Measurement Capture Register 1  */
#define GPTA0_DCMCAV2	(*(GPTA0_DCMCAV0_type*) 0xf00018a8u)	/* GPTA0 Duty Cycle Measurement Capture Register 2  */
#define GPTA0_DCMCAV3	(*(GPTA0_DCMCAV0_type*) 0xf00018b8u)	/* GPTA0 Duty Cycle Measurement Capture Register 3  */

typedef volatile union
{
	struct
	{ 
		unsigned int COV            : 24;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} GPTA0_DCMCOV0_type;
#define GPTA0_DCMCOV0	(*(GPTA0_DCMCOV0_type*) 0xf000188cu)	/* GPTA0 Duty Cycle Measurement Capture/Compare Register 0  */
#define GPTA0_DCMCOV1	(*(GPTA0_DCMCOV0_type*) 0xf000189cu)	/* GPTA0 Duty Cycle Measurement Capture/Compare Register 1  */
#define GPTA0_DCMCOV2	(*(GPTA0_DCMCOV0_type*) 0xf00018acu)	/* GPTA0 Duty Cycle Measurement Capture/Compare Register 2  */
#define GPTA0_DCMCOV3	(*(GPTA0_DCMCOV0_type*) 0xf00018bcu)	/* GPTA0 Duty Cycle Measurement Capture/Compare Register 3  */

typedef volatile union
{
	struct
	{ 
		unsigned int RCA            : 1;
		unsigned int OCA            : 1;
		unsigned int RZE            : 1;
		unsigned int FZE            : 1;
		unsigned int RCK            : 1;
		unsigned int FCK            : 1;
		unsigned int QCK            : 1;
		unsigned int RRE            : 1;
		unsigned int FRE            : 1;
		unsigned int CRE            : 1;
		unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} GPTA0_DCMCTR0_type;
#define GPTA0_DCMCTR0	(*(GPTA0_DCMCTR0_type*) 0xf0001880u)	/* GPTA0 Duty Cycle Measurement Control Register 0  */
#define GPTA0_DCMCTR1	(*(GPTA0_DCMCTR0_type*) 0xf0001890u)	/* GPTA0 Duty Cycle Measurement Control Register 1  */
#define GPTA0_DCMCTR2	(*(GPTA0_DCMCTR0_type*) 0xf00018a0u)	/* GPTA0 Duty Cycle Measurement Control Register 2  */
#define GPTA0_DCMCTR3	(*(GPTA0_DCMCTR0_type*) 0xf00018b0u)	/* GPTA0 Duty Cycle Measurement Control Register 3  */

typedef volatile union
{
	struct
	{ 
		unsigned int TIM            : 24;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} GPTA0_DCMTIM0_type;
#define GPTA0_DCMTIM0	(*(GPTA0_DCMTIM0_type*) 0xf0001884u)	/* GPTA0 Duty Cycle Measurement Timer Register 0  */
#define GPTA0_DCMTIM1	(*(GPTA0_DCMTIM0_type*) 0xf0001894u)	/* GPTA0 Duty Cycle Measurement Timer Register 1  */
#define GPTA0_DCMTIM2	(*(GPTA0_DCMTIM0_type*) 0xf00018a4u)	/* GPTA0 Duty Cycle Measurement Timer Register 2  */
#define GPTA0_DCMTIM3	(*(GPTA0_DCMTIM0_type*) 0xf00018b4u)	/* GPTA0 Duty Cycle Measurement Timer Register 3  */
#define GPTA0_GTTIM0	(*(GPTA0_DCMTIM0_type*) 0xf00018e8u)	/* GPTA0 Global Timer Register 0  */
#define GPTA0_GTTIM1	(*(GPTA0_DCMTIM0_type*) 0xf00018f8u)	/* GPTA0 Global Timer Register 1  */

typedef volatile union
{
	struct
	{ 
		unsigned int GT00RUN        : 1;
		unsigned int GT01RUN        : 1;
		unsigned int                : 6;
		unsigned int G0EN           : 1;
		unsigned int                : 1;
		unsigned int L2EN           : 1;
		unsigned int                : 21;
	} B;
	int I;
	unsigned int U;

} GPTA0_EDCTR_type;
#define GPTA0_EDCTR	(*(GPTA0_EDCTR_type*) 0xf0001c00u)	/* GPTA Clock Enable/Disable Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STEP           : 10;
		unsigned int                : 1;
		unsigned int SM             : 1;
		unsigned int SC             : 2;
		unsigned int DM             : 2;
		/* const */ unsigned int RESULT         : 10;
		unsigned int                : 2;
		/* const */ unsigned int SUSACK         : 1;
		/* const */ unsigned int SUSREQ         : 1;
		unsigned int ENHW           : 1;
		unsigned int DISCLK         : 1;
	} B;
	int I;
	unsigned int U;

} GPTA0_FDR_type;
#define GPTA0_FDR	(*(GPTA0_FDR_type*) 0xf000180cu)	/* GPTA Fractional Divider Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CMP            : 16;
		unsigned int MOD            : 3;
		unsigned int IPS            : 3;
		unsigned int CLK            : 2;
		unsigned int RTG            : 1;
		unsigned int                : 7;
	} B;
	int I;
	unsigned int U;

} GPTA0_FPCCTR0_type;
#define GPTA0_FPCCTR0	(*(GPTA0_FPCCTR0_type*) 0xf0001848u)	/* GPTA0 Filter and Prescaler Cell Control Register 0  */
#define GPTA0_FPCCTR1	(*(GPTA0_FPCCTR0_type*) 0xf0001850u)	/* GPTA0 Filter and Prescaler Cell Control Register 1  */
#define GPTA0_FPCCTR2	(*(GPTA0_FPCCTR0_type*) 0xf0001858u)	/* GPTA0 Filter and Prescaler Cell Control Register 2  */
#define GPTA0_FPCCTR3	(*(GPTA0_FPCCTR0_type*) 0xf0001860u)	/* GPTA0 Filter and Prescaler Cell Control Register 3  */
#define GPTA0_FPCCTR4	(*(GPTA0_FPCCTR0_type*) 0xf0001868u)	/* GPTA0 Filter and Prescaler Cell Control Register 4  */
#define GPTA0_FPCCTR5	(*(GPTA0_FPCCTR0_type*) 0xf0001870u)	/* GPTA0 Filter and Prescaler Cell Control Register 5  */

typedef volatile union
{
	struct
	{ 
		unsigned int REG0           : 1;
		unsigned int REG1           : 1;
		unsigned int REG2           : 1;
		unsigned int REG3           : 1;
		unsigned int REG4           : 1;
		unsigned int REG5           : 1;
		unsigned int                : 2;
		unsigned int FEG0           : 1;
		unsigned int FEG1           : 1;
		unsigned int FEG2           : 1;
		unsigned int FEG3           : 1;
		unsigned int FEG4           : 1;
		unsigned int FEG5           : 1;
		unsigned int                : 18;
	} B;
	int I;
	unsigned int U;

} GPTA0_FPCSTAT_type;
#define GPTA0_FPCSTAT	(*(GPTA0_FPCSTAT_type*) 0xf0001844u)	/* GPTA0 Filter and Prescaler Cell Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int TIM            : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_FPCTIM0_type;
#define GPTA0_FPCTIM0	(*(GPTA0_FPCTIM0_type*) 0xf000184cu)	/* GPTA0 Filter and Prescaler Cell Timer Register 0  */
#define GPTA0_FPCTIM1	(*(GPTA0_FPCTIM0_type*) 0xf0001854u)	/* GPTA0 Filter and Prescaler Cell Timer Register 1  */
#define GPTA0_FPCTIM2	(*(GPTA0_FPCTIM0_type*) 0xf000185cu)	/* GPTA0 Filter and Prescaler Cell Timer Register 2  */
#define GPTA0_FPCTIM3	(*(GPTA0_FPCTIM0_type*) 0xf0001864u)	/* GPTA0 Filter and Prescaler Cell Timer Register 3  */
#define GPTA0_FPCTIM4	(*(GPTA0_FPCTIM0_type*) 0xf000186cu)	/* GPTA0 Filter and Prescaler Cell Timer Register 4  */
#define GPTA0_FPCTIM5	(*(GPTA0_FPCTIM0_type*) 0xf0001874u)	/* GPTA0 Filter and Prescaler Cell Timer Register 5  */

typedef volatile union
{
	struct
	{ 
		unsigned int MOD            : 2;
		unsigned int OSM            : 1;
		unsigned int REN            : 1;
		unsigned int RED            : 1;
		unsigned int FED            : 1;
		unsigned int NE             : 1;
		unsigned int BYP            : 1;
		unsigned int EOA            : 1;
		unsigned int                : 1;
		/* const */ unsigned int CEN            : 1;
		unsigned int OCM            : 3;
		unsigned int OIA            : 1;
		/* const */ unsigned int OUT            : 1;
		unsigned int                : 16;
	} B1;
	struct
	{ 
		unsigned int MOD            : 2;
		unsigned int OSM            : 1;
		unsigned int REN            : 1;
		unsigned int GES            : 1;
		unsigned int CAC            : 1;
		unsigned int CAT            : 1;
		unsigned int BYP            : 1;
		unsigned int EOA            : 1;
		unsigned int                : 1;
		/* const */ unsigned int CEN            : 1;
		unsigned int OCM            : 3;
		unsigned int OIA            : 1;
		/* const */ unsigned int OUT            : 1;
		unsigned int                : 16;
	} B2;
	int I;
	unsigned int U;

} GPTA0_GTCCTR00_type;
#define GPTA0_GTCCTR00	(*(GPTA0_GTCCTR00_type*) 0xf0001900u)	/* GPTA0 Global Timer Cell Control Register 00 [Capture Mode]  */
#define GPTA0_GTCCTR01	(*(GPTA0_GTCCTR00_type*) 0xf0001908u)	/* GPTA0 Global Timer Cell Control Register 01 [Capture Mode]  */
#define GPTA0_GTCCTR02	(*(GPTA0_GTCCTR00_type*) 0xf0001910u)	/* GPTA0 Global Timer Cell Control Register 02 [Capture Mode]  */
#define GPTA0_GTCCTR03	(*(GPTA0_GTCCTR00_type*) 0xf0001918u)	/* GPTA0 Global Timer Cell Control Register 03 [Capture Mode]  */
#define GPTA0_GTCCTR04	(*(GPTA0_GTCCTR00_type*) 0xf0001920u)	/* GPTA0 Global Timer Cell Control Register 04 [Capture Mode]  */
#define GPTA0_GTCCTR05	(*(GPTA0_GTCCTR00_type*) 0xf0001928u)	/* GPTA0 Global Timer Cell Control Register 05 [Capture Mode]  */
#define GPTA0_GTCCTR06	(*(GPTA0_GTCCTR00_type*) 0xf0001930u)	/* GPTA0 Global Timer Cell Control Register 06 [Capture Mode]  */
#define GPTA0_GTCCTR07	(*(GPTA0_GTCCTR00_type*) 0xf0001938u)	/* GPTA0 Global Timer Cell Control Register 07 [Capture Mode]  */
#define GPTA0_GTCCTR08	(*(GPTA0_GTCCTR00_type*) 0xf0001940u)	/* GPTA0 Global Timer Cell Control Register 08 [Capture Mode]  */
#define GPTA0_GTCCTR09	(*(GPTA0_GTCCTR00_type*) 0xf0001948u)	/* GPTA0 Global Timer Cell Control Register 09 [Capture Mode]  */
#define GPTA0_GTCCTR10	(*(GPTA0_GTCCTR00_type*) 0xf0001950u)	/* GPTA0 Global Timer Cell Control Register 10 [Capture Mode]  */
#define GPTA0_GTCCTR11	(*(GPTA0_GTCCTR00_type*) 0xf0001958u)	/* GPTA0 Global Timer Cell Control Register 11 [Capture Mode]  */
#define GPTA0_GTCCTR12	(*(GPTA0_GTCCTR00_type*) 0xf0001960u)	/* GPTA0 Global Timer Cell Control Register 12 [Capture Mode]  */
#define GPTA0_GTCCTR13	(*(GPTA0_GTCCTR00_type*) 0xf0001968u)	/* GPTA0 Global Timer Cell Control Register 13 [Capture Mode]  */
#define GPTA0_GTCCTR14	(*(GPTA0_GTCCTR00_type*) 0xf0001970u)	/* GPTA0 Global Timer Cell Control Register 14 [Capture Mode]  */
#define GPTA0_GTCCTR15	(*(GPTA0_GTCCTR00_type*) 0xf0001978u)	/* GPTA0 Global Timer Cell Control Register 15 [Capture Mode]  */
#define GPTA0_GTCCTR16	(*(GPTA0_GTCCTR00_type*) 0xf0001980u)	/* GPTA0 Global Timer Cell Control Register 16 [Capture Mode]  */
#define GPTA0_GTCCTR17	(*(GPTA0_GTCCTR00_type*) 0xf0001988u)	/* GPTA0 Global Timer Cell Control Register 17 [Capture Mode]  */
#define GPTA0_GTCCTR18	(*(GPTA0_GTCCTR00_type*) 0xf0001990u)	/* GPTA0 Global Timer Cell Control Register 18 [Capture Mode]  */
#define GPTA0_GTCCTR19	(*(GPTA0_GTCCTR00_type*) 0xf0001998u)	/* GPTA0 Global Timer Cell Control Register 19 [Capture Mode]  */
#define GPTA0_GTCCTR20	(*(GPTA0_GTCCTR00_type*) 0xf00019a0u)	/* GPTA0 Global Timer Cell Control Register 20 [Capture Mode]  */
#define GPTA0_GTCCTR21	(*(GPTA0_GTCCTR00_type*) 0xf00019a8u)	/* GPTA0 Global Timer Cell Control Register 21 [Capture Mode]  */
#define GPTA0_GTCCTR22	(*(GPTA0_GTCCTR00_type*) 0xf00019b0u)	/* GPTA0 Global Timer Cell Control Register 22 [Capture Mode]  */
#define GPTA0_GTCCTR23	(*(GPTA0_GTCCTR00_type*) 0xf00019b8u)	/* GPTA0 Global Timer Cell Control Register 23 [Capture Mode]  */
#define GPTA0_GTCCTR24	(*(GPTA0_GTCCTR00_type*) 0xf00019c0u)	/* GPTA0 Global Timer Cell Control Register 24 [Capture Mode]  */
#define GPTA0_GTCCTR25	(*(GPTA0_GTCCTR00_type*) 0xf00019c8u)	/* GPTA0 Global Timer Cell Control Register 25 [Capture Mode]  */
#define GPTA0_GTCCTR26	(*(GPTA0_GTCCTR00_type*) 0xf00019d0u)	/* GPTA0 Global Timer Cell Control Register 26 [Capture Mode]  */
#define GPTA0_GTCCTR27	(*(GPTA0_GTCCTR00_type*) 0xf00019d8u)	/* GPTA0 Global Timer Cell Control Register 27 [Capture Mode]  */
#define GPTA0_GTCCTR28	(*(GPTA0_GTCCTR00_type*) 0xf00019e0u)	/* GPTA0 Global Timer Cell Control Register 28 [Capture Mode]  */
#define GPTA0_GTCCTR29	(*(GPTA0_GTCCTR00_type*) 0xf00019e8u)	/* GPTA0 Global Timer Cell Control Register 29 [Capture Mode]  */
#define GPTA0_GTCCTR30	(*(GPTA0_GTCCTR00_type*) 0xf00019f0u)	/* GPTA0 Global Timer Cell Control Register 30 [Capture Mode]  */
#define GPTA0_GTCCTR31	(*(GPTA0_GTCCTR00_type*) 0xf00019f8u)	/* GPTA0 Global Timer Cell Control Register 31 [Capture Mode]  */

typedef volatile union
{
	struct
	{ 
		unsigned int SCO            : 4;
		unsigned int MUX            : 3;
		unsigned int REN            : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} GPTA0_GTCTR0_type;
#define GPTA0_GTCTR0	(*(GPTA0_GTCTR0_type*) 0xf00018e0u)	/* GPTA0 Global Timer Control Register 0  */
#define GPTA0_GTCTR1	(*(GPTA0_GTCTR0_type*) 0xf00018f0u)	/* GPTA0 Global Timer Control Register 1  */

typedef volatile union
{
	struct
	{ 
		unsigned int X              : 24;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} GPTA0_GTCXR00_type;
#define GPTA0_GTCXR00	(*(GPTA0_GTCXR00_type*) 0xf0001904u)	/* GPTA0 Global Timer Cell X Register 00  */
#define GPTA0_GTCXR01	(*(GPTA0_GTCXR00_type*) 0xf000190cu)	/* GPTA0 Global Timer Cell X Register 01  */
#define GPTA0_GTCXR02	(*(GPTA0_GTCXR00_type*) 0xf0001914u)	/* GPTA0 Global Timer Cell X Register 02  */
#define GPTA0_GTCXR03	(*(GPTA0_GTCXR00_type*) 0xf000191cu)	/* GPTA0 Global Timer Cell X Register 03  */
#define GPTA0_GTCXR04	(*(GPTA0_GTCXR00_type*) 0xf0001924u)	/* GPTA0 Global Timer Cell X Register 04  */
#define GPTA0_GTCXR05	(*(GPTA0_GTCXR00_type*) 0xf000192cu)	/* GPTA0 Global Timer Cell X Register 05  */
#define GPTA0_GTCXR06	(*(GPTA0_GTCXR00_type*) 0xf0001934u)	/* GPTA0 Global Timer Cell X Register 06  */
#define GPTA0_GTCXR07	(*(GPTA0_GTCXR00_type*) 0xf000193cu)	/* GPTA0 Global Timer Cell X Register 07  */
#define GPTA0_GTCXR08	(*(GPTA0_GTCXR00_type*) 0xf0001944u)	/* GPTA0 Global Timer Cell X Register 08  */
#define GPTA0_GTCXR09	(*(GPTA0_GTCXR00_type*) 0xf000194cu)	/* GPTA0 Global Timer Cell X Register 09  */
#define GPTA0_GTCXR10	(*(GPTA0_GTCXR00_type*) 0xf0001954u)	/* GPTA0 Global Timer Cell X Register 10  */
#define GPTA0_GTCXR11	(*(GPTA0_GTCXR00_type*) 0xf000195cu)	/* GPTA0 Global Timer Cell X Register 11  */
#define GPTA0_GTCXR12	(*(GPTA0_GTCXR00_type*) 0xf0001964u)	/* GPTA0 Global Timer Cell X Register 12  */
#define GPTA0_GTCXR13	(*(GPTA0_GTCXR00_type*) 0xf000196cu)	/* GPTA0 Global Timer Cell X Register 13  */
#define GPTA0_GTCXR14	(*(GPTA0_GTCXR00_type*) 0xf0001974u)	/* GPTA0 Global Timer Cell X Register 14  */
#define GPTA0_GTCXR15	(*(GPTA0_GTCXR00_type*) 0xf000197cu)	/* GPTA0 Global Timer Cell X Register 15  */
#define GPTA0_GTCXR16	(*(GPTA0_GTCXR00_type*) 0xf0001984u)	/* GPTA0 Global Timer Cell X Register 16  */
#define GPTA0_GTCXR17	(*(GPTA0_GTCXR00_type*) 0xf000198cu)	/* GPTA0 Global Timer Cell X Register 17  */
#define GPTA0_GTCXR18	(*(GPTA0_GTCXR00_type*) 0xf0001994u)	/* GPTA0 Global Timer Cell X Register 18  */
#define GPTA0_GTCXR19	(*(GPTA0_GTCXR00_type*) 0xf000199cu)	/* GPTA0 Global Timer Cell X Register 19  */
#define GPTA0_GTCXR20	(*(GPTA0_GTCXR00_type*) 0xf00019a4u)	/* GPTA0 Global Timer Cell X Register 20  */
#define GPTA0_GTCXR21	(*(GPTA0_GTCXR00_type*) 0xf00019acu)	/* GPTA0 Global Timer Cell X Register 21  */
#define GPTA0_GTCXR22	(*(GPTA0_GTCXR00_type*) 0xf00019b4u)	/* GPTA0 Global Timer Cell X Register 22  */
#define GPTA0_GTCXR23	(*(GPTA0_GTCXR00_type*) 0xf00019bcu)	/* GPTA0 Global Timer Cell X Register 23  */
#define GPTA0_GTCXR24	(*(GPTA0_GTCXR00_type*) 0xf00019c4u)	/* GPTA0 Global Timer Cell X Register 24  */
#define GPTA0_GTCXR25	(*(GPTA0_GTCXR00_type*) 0xf00019ccu)	/* GPTA0 Global Timer Cell X Register 25  */
#define GPTA0_GTCXR26	(*(GPTA0_GTCXR00_type*) 0xf00019d4u)	/* GPTA0 Global Timer Cell X Register 26  */
#define GPTA0_GTCXR27	(*(GPTA0_GTCXR00_type*) 0xf00019dcu)	/* GPTA0 Global Timer Cell X Register 27  */
#define GPTA0_GTCXR28	(*(GPTA0_GTCXR00_type*) 0xf00019e4u)	/* GPTA0 Global Timer Cell X Register 28  */
#define GPTA0_GTCXR29	(*(GPTA0_GTCXR00_type*) 0xf00019ecu)	/* GPTA0 Global Timer Cell X Register 29  */
#define GPTA0_GTCXR30	(*(GPTA0_GTCXR00_type*) 0xf00019f4u)	/* GPTA0 Global Timer Cell X Register 30  */
#define GPTA0_GTCXR31	(*(GPTA0_GTCXR00_type*) 0xf00019fcu)	/* GPTA0 Global Timer Cell X Register 31  */

typedef volatile union
{
	struct
	{ 
		unsigned int REV            : 24;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} GPTA0_GTREV0_type;
#define GPTA0_GTREV0	(*(GPTA0_GTREV0_type*) 0xf00018e4u)	/* GPTA0 Global Timer Reload Value Register 0  */
#define GPTA0_GTREV1	(*(GPTA0_GTREV0_type*) 0xf00018f4u)	/* GPTA0 Global Timer Reload Value Register 1  */
#define GPTA0_PLLREV	(*(GPTA0_GTREV0_type*) 0xf00018d0u)	/* GPTA0 Phase Locked Loop Reload Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int MOD_REV        : 8;
		/* const */ unsigned int MOD_TYPE       : 8;
		/* const */ unsigned int MOD_NUM        : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_ID_type;
#define GPTA0_ID	(*(GPTA0_ID_type*) 0xf0001808u)	/* GPTA0 Identification Register  */
#define LTCA2_ID	(*(GPTA0_ID_type*) 0xf0002808u)	/* LTCA2 Identification Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MOD            : 2;
		unsigned int OSM            : 1;
		unsigned int REN            : 1;
		unsigned int PEN            : 1;
		unsigned int AIL            : 1;
		unsigned int SLO            : 1;
		unsigned int CUDCLR         : 1;
		unsigned int ILM            : 1;
		unsigned int CUD            : 1;
		/* const */ unsigned int CEN            : 1;
		unsigned int OCM            : 3;
		unsigned int OIA            : 1;
		/* const */ unsigned int OUT            : 1;
		unsigned int GBYP           : 1;
		unsigned int                : 15;
	} B1;
	struct
	{ 
		unsigned int MOD            : 2;
		unsigned int OSM            : 1;
		unsigned int REN            : 1;
		unsigned int RED            : 1;
		unsigned int FED            : 1;
		unsigned int BYP            : 1;
		unsigned int EOA            : 1;
		unsigned int ILM            : 1;
		/* const */ unsigned int SLL            : 1;
		/* const */ unsigned int CEN            : 1;
		unsigned int OCM            : 3;
		unsigned int OIA            : 1;
		/* const */ unsigned int OUT            : 1;
		unsigned int GBYP           : 1;
		unsigned int                : 15;
	} B2;
	struct
	{ 
		unsigned int MOD            : 2;
		unsigned int OSM            : 1;
		unsigned int REN            : 1;
		unsigned int SOL            : 1;
		unsigned int SOH            : 1;
		unsigned int BYP            : 1;
		unsigned int EOA            : 1;
		unsigned int ILM            : 1;
		/* const */ unsigned int SLL            : 1;
		/* const */ unsigned int CEN            : 1;
		unsigned int OCM            : 3;
		unsigned int OIA            : 1;
		/* const */ unsigned int OUT            : 1;
		unsigned int GBYP           : 1;
		unsigned int                : 15;
	} B3;
	int I;
	unsigned int U;

} GPTA0_LTCCTR00_type;
#define GPTA0_LTCCTR00	(*(GPTA0_LTCCTR00_type*) 0xf0001a00u)	/* GPTA0 Local Timer Cell Control Register 00 [Timer Mode]  */
#define GPTA0_LTCCTR01	(*(GPTA0_LTCCTR00_type*) 0xf0001a08u)	/* GPTA0 Local Timer Cell Control Register 01 [Timer Mode]  */
#define GPTA0_LTCCTR02	(*(GPTA0_LTCCTR00_type*) 0xf0001a10u)	/* GPTA0 Local Timer Cell Control Register 02 [Timer Mode]  */
#define GPTA0_LTCCTR03	(*(GPTA0_LTCCTR00_type*) 0xf0001a18u)	/* GPTA0 Local Timer Cell Control Register 03 [Timer Mode]  */
#define GPTA0_LTCCTR04	(*(GPTA0_LTCCTR00_type*) 0xf0001a20u)	/* GPTA0 Local Timer Cell Control Register 04 [Timer Mode]  */
#define GPTA0_LTCCTR05	(*(GPTA0_LTCCTR00_type*) 0xf0001a28u)	/* GPTA0 Local Timer Cell Control Register 05 [Timer Mode]  */
#define GPTA0_LTCCTR06	(*(GPTA0_LTCCTR00_type*) 0xf0001a30u)	/* GPTA0 Local Timer Cell Control Register 06 [Timer Mode]  */
#define GPTA0_LTCCTR07	(*(GPTA0_LTCCTR00_type*) 0xf0001a38u)	/* GPTA0 Local Timer Cell Control Register 07 [Timer Mode]  */
#define GPTA0_LTCCTR08	(*(GPTA0_LTCCTR00_type*) 0xf0001a40u)	/* GPTA0 Local Timer Cell Control Register 08 [Timer Mode]  */
#define GPTA0_LTCCTR09	(*(GPTA0_LTCCTR00_type*) 0xf0001a48u)	/* GPTA0 Local Timer Cell Control Register 09 [Timer Mode]  */
#define GPTA0_LTCCTR10	(*(GPTA0_LTCCTR00_type*) 0xf0001a50u)	/* GPTA0 Local Timer Cell Control Register 10 [Timer Mode]  */
#define GPTA0_LTCCTR11	(*(GPTA0_LTCCTR00_type*) 0xf0001a58u)	/* GPTA0 Local Timer Cell Control Register 11 [Timer Mode]  */
#define GPTA0_LTCCTR12	(*(GPTA0_LTCCTR00_type*) 0xf0001a60u)	/* GPTA0 Local Timer Cell Control Register 12 [Timer Mode]  */
#define GPTA0_LTCCTR13	(*(GPTA0_LTCCTR00_type*) 0xf0001a68u)	/* GPTA0 Local Timer Cell Control Register 13 [Timer Mode]  */
#define GPTA0_LTCCTR14	(*(GPTA0_LTCCTR00_type*) 0xf0001a70u)	/* GPTA0 Local Timer Cell Control Register 14 [Timer Mode]  */
#define GPTA0_LTCCTR15	(*(GPTA0_LTCCTR00_type*) 0xf0001a78u)	/* GPTA0 Local Timer Cell Control Register 15 [Timer Mode]  */
#define GPTA0_LTCCTR16	(*(GPTA0_LTCCTR00_type*) 0xf0001a80u)	/* GPTA0 Local Timer Cell Control Register 16 [Timer Mode]  */
#define GPTA0_LTCCTR17	(*(GPTA0_LTCCTR00_type*) 0xf0001a88u)	/* GPTA0 Local Timer Cell Control Register 17 [Timer Mode]  */
#define GPTA0_LTCCTR18	(*(GPTA0_LTCCTR00_type*) 0xf0001a90u)	/* GPTA0 Local Timer Cell Control Register 18 [Timer Mode]  */
#define GPTA0_LTCCTR19	(*(GPTA0_LTCCTR00_type*) 0xf0001a98u)	/* GPTA0 Local Timer Cell Control Register 19 [Timer Mode]  */
#define GPTA0_LTCCTR20	(*(GPTA0_LTCCTR00_type*) 0xf0001aa0u)	/* GPTA0 Local Timer Cell Control Register 20 [Timer Mode]  */
#define GPTA0_LTCCTR21	(*(GPTA0_LTCCTR00_type*) 0xf0001aa8u)	/* GPTA0 Local Timer Cell Control Register 21 [Timer Mode]  */
#define GPTA0_LTCCTR22	(*(GPTA0_LTCCTR00_type*) 0xf0001ab0u)	/* GPTA0 Local Timer Cell Control Register 22 [Timer Mode]  */
#define GPTA0_LTCCTR23	(*(GPTA0_LTCCTR00_type*) 0xf0001ab8u)	/* GPTA0 Local Timer Cell Control Register 23 [Timer Mode]  */
#define GPTA0_LTCCTR24	(*(GPTA0_LTCCTR00_type*) 0xf0001ac0u)	/* GPTA0 Local Timer Cell Control Register 24 [Timer Mode]  */
#define GPTA0_LTCCTR25	(*(GPTA0_LTCCTR00_type*) 0xf0001ac8u)	/* GPTA0 Local Timer Cell Control Register 25 [Timer Mode]  */
#define GPTA0_LTCCTR26	(*(GPTA0_LTCCTR00_type*) 0xf0001ad0u)	/* GPTA0 Local Timer Cell Control Register 26 [Timer Mode]  */
#define GPTA0_LTCCTR27	(*(GPTA0_LTCCTR00_type*) 0xf0001ad8u)	/* GPTA0 Local Timer Cell Control Register 27 [Timer Mode]  */
#define GPTA0_LTCCTR28	(*(GPTA0_LTCCTR00_type*) 0xf0001ae0u)	/* GPTA0 Local Timer Cell Control Register 28 [Timer Mode]  */
#define GPTA0_LTCCTR29	(*(GPTA0_LTCCTR00_type*) 0xf0001ae8u)	/* GPTA0 Local Timer Cell Control Register 29 [Timer Mode]  */
#define GPTA0_LTCCTR30	(*(GPTA0_LTCCTR00_type*) 0xf0001af0u)	/* GPTA0 Local Timer Cell Control Register 30 [Timer Mode]  */
#define GPTA0_LTCCTR31	(*(GPTA0_LTCCTR00_type*) 0xf0001af8u)	/* GPTA0 Local Timer Cell Control Register 31 [Timer Mode]  */
#define GPTA0_LTCCTR32	(*(GPTA0_LTCCTR00_type*) 0xf0001b00u)	/* GPTA0 Local Timer Cell Control Register 32 [Timer Mode]  */
#define GPTA0_LTCCTR33	(*(GPTA0_LTCCTR00_type*) 0xf0001b08u)	/* GPTA0 Local Timer Cell Control Register 33 [Timer Mode]  */
#define GPTA0_LTCCTR34	(*(GPTA0_LTCCTR00_type*) 0xf0001b10u)	/* GPTA0 Local Timer Cell Control Register 34 [Timer Mode]  */
#define GPTA0_LTCCTR35	(*(GPTA0_LTCCTR00_type*) 0xf0001b18u)	/* GPTA0 Local Timer Cell Control Register 35 [Timer Mode]  */
#define GPTA0_LTCCTR36	(*(GPTA0_LTCCTR00_type*) 0xf0001b20u)	/* GPTA0 Local Timer Cell Control Register 36 [Timer Mode]  */
#define GPTA0_LTCCTR37	(*(GPTA0_LTCCTR00_type*) 0xf0001b28u)	/* GPTA0 Local Timer Cell Control Register 37 [Timer Mode]  */
#define GPTA0_LTCCTR38	(*(GPTA0_LTCCTR00_type*) 0xf0001b30u)	/* GPTA0 Local Timer Cell Control Register 38 [Timer Mode]  */
#define GPTA0_LTCCTR39	(*(GPTA0_LTCCTR00_type*) 0xf0001b38u)	/* GPTA0 Local Timer Cell Control Register 39 [Timer Mode]  */
#define GPTA0_LTCCTR40	(*(GPTA0_LTCCTR00_type*) 0xf0001b40u)	/* GPTA0 Local Timer Cell Control Register 40 [Timer Mode]  */
#define GPTA0_LTCCTR41	(*(GPTA0_LTCCTR00_type*) 0xf0001b48u)	/* GPTA0 Local Timer Cell Control Register 41 [Timer Mode]  */
#define GPTA0_LTCCTR42	(*(GPTA0_LTCCTR00_type*) 0xf0001b50u)	/* GPTA0 Local Timer Cell Control Register 42 [Timer Mode]  */
#define GPTA0_LTCCTR43	(*(GPTA0_LTCCTR00_type*) 0xf0001b58u)	/* GPTA0 Local Timer Cell Control Register 43 [Timer Mode]  */
#define GPTA0_LTCCTR44	(*(GPTA0_LTCCTR00_type*) 0xf0001b60u)	/* GPTA0 Local Timer Cell Control Register 44 [Timer Mode]  */
#define GPTA0_LTCCTR45	(*(GPTA0_LTCCTR00_type*) 0xf0001b68u)	/* GPTA0 Local Timer Cell Control Register 45 [Timer Mode]  */
#define GPTA0_LTCCTR46	(*(GPTA0_LTCCTR00_type*) 0xf0001b70u)	/* GPTA0 Local Timer Cell Control Register 46 [Timer Mode]  */
#define GPTA0_LTCCTR47	(*(GPTA0_LTCCTR00_type*) 0xf0001b78u)	/* GPTA0 Local Timer Cell Control Register 47 [Timer Mode]  */
#define GPTA0_LTCCTR48	(*(GPTA0_LTCCTR00_type*) 0xf0001b80u)	/* GPTA0 Local Timer Cell Control Register 48 [Timer Mode]  */
#define GPTA0_LTCCTR49	(*(GPTA0_LTCCTR00_type*) 0xf0001b88u)	/* GPTA0 Local Timer Cell Control Register 49 [Timer Mode]  */
#define GPTA0_LTCCTR50	(*(GPTA0_LTCCTR00_type*) 0xf0001b90u)	/* GPTA0 Local Timer Cell Control Register 50 [Timer Mode]  */
#define GPTA0_LTCCTR51	(*(GPTA0_LTCCTR00_type*) 0xf0001b98u)	/* GPTA0 Local Timer Cell Control Register 51 [Timer Mode]  */
#define GPTA0_LTCCTR52	(*(GPTA0_LTCCTR00_type*) 0xf0001ba0u)	/* GPTA0 Local Timer Cell Control Register 52 [Timer Mode]  */
#define GPTA0_LTCCTR53	(*(GPTA0_LTCCTR00_type*) 0xf0001ba8u)	/* GPTA0 Local Timer Cell Control Register 53 [Timer Mode]  */
#define GPTA0_LTCCTR54	(*(GPTA0_LTCCTR00_type*) 0xf0001bb0u)	/* GPTA0 Local Timer Cell Control Register 54 [Timer Mode]  */
#define GPTA0_LTCCTR55	(*(GPTA0_LTCCTR00_type*) 0xf0001bb8u)	/* GPTA0 Local Timer Cell Control Register 55 [Timer Mode]  */
#define GPTA0_LTCCTR56	(*(GPTA0_LTCCTR00_type*) 0xf0001bc0u)	/* GPTA0 Local Timer Cell Control Register 56 [Timer Mode]  */
#define GPTA0_LTCCTR57	(*(GPTA0_LTCCTR00_type*) 0xf0001bc8u)	/* GPTA0 Local Timer Cell Control Register 57 [Timer Mode]  */
#define GPTA0_LTCCTR58	(*(GPTA0_LTCCTR00_type*) 0xf0001bd0u)	/* GPTA0 Local Timer Cell Control Register 58 [Timer Mode]  */
#define GPTA0_LTCCTR59	(*(GPTA0_LTCCTR00_type*) 0xf0001bd8u)	/* GPTA0 Local Timer Cell Control Register 59 [Timer Mode]  */
#define GPTA0_LTCCTR60	(*(GPTA0_LTCCTR00_type*) 0xf0001be0u)	/* GPTA0 Local Timer Cell Control Register 60 [Timer Mode]  */
#define GPTA0_LTCCTR61	(*(GPTA0_LTCCTR00_type*) 0xf0001be8u)	/* GPTA0 Local Timer Cell Control Register 61 [Timer Mode]  */
#define GPTA0_LTCCTR62	(*(GPTA0_LTCCTR00_type*) 0xf0001bf0u)	/* GPTA0 Local Timer Cell Control Register 62 [Timer Mode]  */
#define LTCA2_LTCCTR00	(*(GPTA0_LTCCTR00_type*) 0xf0002a00u)	/* Local Timer Cell Control Register 00 [Timer Mode]  */
#define LTCA2_LTCCTR01	(*(GPTA0_LTCCTR00_type*) 0xf0002a08u)	/* Local Timer Cell Control Register 01 [Timer Mode]  */
#define LTCA2_LTCCTR02	(*(GPTA0_LTCCTR00_type*) 0xf0002a10u)	/* Local Timer Cell Control Register 02 [Timer Mode]  */
#define LTCA2_LTCCTR03	(*(GPTA0_LTCCTR00_type*) 0xf0002a18u)	/* Local Timer Cell Control Register 03 [Timer Mode]  */
#define LTCA2_LTCCTR04	(*(GPTA0_LTCCTR00_type*) 0xf0002a20u)	/* Local Timer Cell Control Register 04 [Timer Mode]  */
#define LTCA2_LTCCTR05	(*(GPTA0_LTCCTR00_type*) 0xf0002a28u)	/* Local Timer Cell Control Register 05 [Timer Mode]  */
#define LTCA2_LTCCTR06	(*(GPTA0_LTCCTR00_type*) 0xf0002a30u)	/* Local Timer Cell Control Register 06 [Timer Mode]  */
#define LTCA2_LTCCTR07	(*(GPTA0_LTCCTR00_type*) 0xf0002a38u)	/* Local Timer Cell Control Register 07 [Timer Mode]  */
#define LTCA2_LTCCTR08	(*(GPTA0_LTCCTR00_type*) 0xf0002a40u)	/* Local Timer Cell Control Register 08 [Timer Mode]  */
#define LTCA2_LTCCTR09	(*(GPTA0_LTCCTR00_type*) 0xf0002a48u)	/* Local Timer Cell Control Register 09 [Timer Mode]  */
#define LTCA2_LTCCTR10	(*(GPTA0_LTCCTR00_type*) 0xf0002a50u)	/* Local Timer Cell Control Register 10 [Timer Mode]  */
#define LTCA2_LTCCTR11	(*(GPTA0_LTCCTR00_type*) 0xf0002a58u)	/* Local Timer Cell Control Register 11 [Timer Mode]  */
#define LTCA2_LTCCTR12	(*(GPTA0_LTCCTR00_type*) 0xf0002a60u)	/* Local Timer Cell Control Register 12 [Timer Mode]  */
#define LTCA2_LTCCTR13	(*(GPTA0_LTCCTR00_type*) 0xf0002a68u)	/* Local Timer Cell Control Register 13 [Timer Mode]  */
#define LTCA2_LTCCTR14	(*(GPTA0_LTCCTR00_type*) 0xf0002a70u)	/* Local Timer Cell Control Register 14 [Timer Mode]  */
#define LTCA2_LTCCTR15	(*(GPTA0_LTCCTR00_type*) 0xf0002a78u)	/* Local Timer Cell Control Register 15 [Timer Mode]  */
#define LTCA2_LTCCTR16	(*(GPTA0_LTCCTR00_type*) 0xf0002a80u)	/* Local Timer Cell Control Register 16 [Timer Mode]  */
#define LTCA2_LTCCTR17	(*(GPTA0_LTCCTR00_type*) 0xf0002a88u)	/* Local Timer Cell Control Register 17 [Timer Mode]  */
#define LTCA2_LTCCTR18	(*(GPTA0_LTCCTR00_type*) 0xf0002a90u)	/* Local Timer Cell Control Register 18 [Timer Mode]  */
#define LTCA2_LTCCTR19	(*(GPTA0_LTCCTR00_type*) 0xf0002a98u)	/* Local Timer Cell Control Register 19 [Timer Mode]  */
#define LTCA2_LTCCTR20	(*(GPTA0_LTCCTR00_type*) 0xf0002aa0u)	/* Local Timer Cell Control Register 20 [Timer Mode]  */
#define LTCA2_LTCCTR21	(*(GPTA0_LTCCTR00_type*) 0xf0002aa8u)	/* Local Timer Cell Control Register 21 [Timer Mode]  */
#define LTCA2_LTCCTR22	(*(GPTA0_LTCCTR00_type*) 0xf0002ab0u)	/* Local Timer Cell Control Register 22 [Timer Mode]  */
#define LTCA2_LTCCTR23	(*(GPTA0_LTCCTR00_type*) 0xf0002ab8u)	/* Local Timer Cell Control Register 23 [Timer Mode]  */
#define LTCA2_LTCCTR24	(*(GPTA0_LTCCTR00_type*) 0xf0002ac0u)	/* Local Timer Cell Control Register 24 [Timer Mode]  */
#define LTCA2_LTCCTR25	(*(GPTA0_LTCCTR00_type*) 0xf0002ac8u)	/* Local Timer Cell Control Register 25 [Timer Mode]  */
#define LTCA2_LTCCTR26	(*(GPTA0_LTCCTR00_type*) 0xf0002ad0u)	/* Local Timer Cell Control Register 26 [Timer Mode]  */
#define LTCA2_LTCCTR27	(*(GPTA0_LTCCTR00_type*) 0xf0002ad8u)	/* Local Timer Cell Control Register 27 [Timer Mode]  */
#define LTCA2_LTCCTR28	(*(GPTA0_LTCCTR00_type*) 0xf0002ae0u)	/* Local Timer Cell Control Register 28 [Timer Mode]  */
#define LTCA2_LTCCTR29	(*(GPTA0_LTCCTR00_type*) 0xf0002ae8u)	/* Local Timer Cell Control Register 29 [Timer Mode]  */
#define LTCA2_LTCCTR30	(*(GPTA0_LTCCTR00_type*) 0xf0002af0u)	/* Local Timer Cell Control Register 30 [Timer Mode]  */

typedef volatile union
{
	struct
	{ 
		unsigned int BRM            : 1;
		unsigned int OSM            : 1;
		unsigned int REN            : 2;
		unsigned int RED            : 1;
		unsigned int FED            : 1;
		unsigned int                : 2;
		unsigned int ILM            : 1;
		unsigned int                : 1;
		/* const */ unsigned int CEN            : 1;
		unsigned int                : 4;
		/* const */ unsigned int OUT            : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_LTCCTR63_type;
#define GPTA0_LTCCTR63	(*(GPTA0_LTCCTR63_type*) 0xf0001bf8u)	/* GPTA0 Local Timer Cell Control Register 63  */
#define LTCA2_LTCCTR31	(*(GPTA0_LTCCTR63_type*) 0xf0002af8u)	/* Local Timer Cell Control Register 31  */

typedef volatile union
{
	struct
	{ 
		unsigned int X              : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_LTCXR00_type;
#define GPTA0_LTCXR00	(*(GPTA0_LTCXR00_type*) 0xf0001a04u)	/* GPTA0 Local Timer Cell X Register 00  */
#define GPTA0_LTCXR01	(*(GPTA0_LTCXR00_type*) 0xf0001a0cu)	/* GPTA0 Local Timer Cell X Register 01  */
#define GPTA0_LTCXR02	(*(GPTA0_LTCXR00_type*) 0xf0001a14u)	/* GPTA0 Local Timer Cell X Register 02  */
#define GPTA0_LTCXR03	(*(GPTA0_LTCXR00_type*) 0xf0001a1cu)	/* GPTA0 Local Timer Cell X Register 03  */
#define GPTA0_LTCXR04	(*(GPTA0_LTCXR00_type*) 0xf0001a24u)	/* GPTA0 Local Timer Cell X Register 04  */
#define GPTA0_LTCXR05	(*(GPTA0_LTCXR00_type*) 0xf0001a2cu)	/* GPTA0 Local Timer Cell X Register 05  */
#define GPTA0_LTCXR06	(*(GPTA0_LTCXR00_type*) 0xf0001a34u)	/* GPTA0 Local Timer Cell X Register 06  */
#define GPTA0_LTCXR07	(*(GPTA0_LTCXR00_type*) 0xf0001a3cu)	/* GPTA0 Local Timer Cell X Register 07  */
#define GPTA0_LTCXR08	(*(GPTA0_LTCXR00_type*) 0xf0001a44u)	/* GPTA0 Local Timer Cell X Register 08  */
#define GPTA0_LTCXR09	(*(GPTA0_LTCXR00_type*) 0xf0001a4cu)	/* GPTA0 Local Timer Cell X Register 09  */
#define GPTA0_LTCXR10	(*(GPTA0_LTCXR00_type*) 0xf0001a54u)	/* GPTA0 Local Timer Cell X Register 10  */
#define GPTA0_LTCXR11	(*(GPTA0_LTCXR00_type*) 0xf0001a5cu)	/* GPTA0 Local Timer Cell X Register 11  */
#define GPTA0_LTCXR12	(*(GPTA0_LTCXR00_type*) 0xf0001a64u)	/* GPTA0 Local Timer Cell X Register 12  */
#define GPTA0_LTCXR13	(*(GPTA0_LTCXR00_type*) 0xf0001a6cu)	/* GPTA0 Local Timer Cell X Register 13  */
#define GPTA0_LTCXR14	(*(GPTA0_LTCXR00_type*) 0xf0001a74u)	/* GPTA0 Local Timer Cell X Register 14  */
#define GPTA0_LTCXR15	(*(GPTA0_LTCXR00_type*) 0xf0001a7cu)	/* GPTA0 Local Timer Cell X Register 15  */
#define GPTA0_LTCXR16	(*(GPTA0_LTCXR00_type*) 0xf0001a84u)	/* GPTA0 Local Timer Cell X Register 16  */
#define GPTA0_LTCXR17	(*(GPTA0_LTCXR00_type*) 0xf0001a8cu)	/* GPTA0 Local Timer Cell X Register 17  */
#define GPTA0_LTCXR18	(*(GPTA0_LTCXR00_type*) 0xf0001a94u)	/* GPTA0 Local Timer Cell X Register 18  */
#define GPTA0_LTCXR19	(*(GPTA0_LTCXR00_type*) 0xf0001a9cu)	/* GPTA0 Local Timer Cell X Register 19  */
#define GPTA0_LTCXR20	(*(GPTA0_LTCXR00_type*) 0xf0001aa4u)	/* GPTA0 Local Timer Cell X Register 20  */
#define GPTA0_LTCXR21	(*(GPTA0_LTCXR00_type*) 0xf0001aacu)	/* GPTA0 Local Timer Cell X Register 21  */
#define GPTA0_LTCXR22	(*(GPTA0_LTCXR00_type*) 0xf0001ab4u)	/* GPTA0 Local Timer Cell X Register 22  */
#define GPTA0_LTCXR23	(*(GPTA0_LTCXR00_type*) 0xf0001abcu)	/* GPTA0 Local Timer Cell X Register 23  */
#define GPTA0_LTCXR24	(*(GPTA0_LTCXR00_type*) 0xf0001ac4u)	/* GPTA0 Local Timer Cell X Register 24  */
#define GPTA0_LTCXR25	(*(GPTA0_LTCXR00_type*) 0xf0001accu)	/* GPTA0 Local Timer Cell X Register 25  */
#define GPTA0_LTCXR26	(*(GPTA0_LTCXR00_type*) 0xf0001ad4u)	/* GPTA0 Local Timer Cell X Register 26  */
#define GPTA0_LTCXR27	(*(GPTA0_LTCXR00_type*) 0xf0001adcu)	/* GPTA0 Local Timer Cell X Register 27  */
#define GPTA0_LTCXR28	(*(GPTA0_LTCXR00_type*) 0xf0001ae4u)	/* GPTA0 Local Timer Cell X Register 28  */
#define GPTA0_LTCXR29	(*(GPTA0_LTCXR00_type*) 0xf0001aecu)	/* GPTA0 Local Timer Cell X Register 29  */
#define GPTA0_LTCXR30	(*(GPTA0_LTCXR00_type*) 0xf0001af4u)	/* GPTA0 Local Timer Cell X Register 30  */
#define GPTA0_LTCXR31	(*(GPTA0_LTCXR00_type*) 0xf0001afcu)	/* GPTA0 Local Timer Cell X Register 31  */
#define GPTA0_LTCXR32	(*(GPTA0_LTCXR00_type*) 0xf0001b04u)	/* GPTA0 Local Timer Cell X Register 32  */
#define GPTA0_LTCXR33	(*(GPTA0_LTCXR00_type*) 0xf0001b0cu)	/* GPTA0 Local Timer Cell X Register 33  */
#define GPTA0_LTCXR34	(*(GPTA0_LTCXR00_type*) 0xf0001b14u)	/* GPTA0 Local Timer Cell X Register 34  */
#define GPTA0_LTCXR35	(*(GPTA0_LTCXR00_type*) 0xf0001b1cu)	/* GPTA0 Local Timer Cell X Register 35  */
#define GPTA0_LTCXR36	(*(GPTA0_LTCXR00_type*) 0xf0001b24u)	/* GPTA0 Local Timer Cell X Register 36  */
#define GPTA0_LTCXR37	(*(GPTA0_LTCXR00_type*) 0xf0001b2cu)	/* GPTA0 Local Timer Cell X Register 37  */
#define GPTA0_LTCXR38	(*(GPTA0_LTCXR00_type*) 0xf0001b34u)	/* GPTA0 Local Timer Cell X Register 38  */
#define GPTA0_LTCXR39	(*(GPTA0_LTCXR00_type*) 0xf0001b3cu)	/* GPTA0 Local Timer Cell X Register 39  */
#define GPTA0_LTCXR40	(*(GPTA0_LTCXR00_type*) 0xf0001b44u)	/* GPTA0 Local Timer Cell X Register 40  */
#define GPTA0_LTCXR41	(*(GPTA0_LTCXR00_type*) 0xf0001b4cu)	/* GPTA0 Local Timer Cell X Register 41  */
#define GPTA0_LTCXR42	(*(GPTA0_LTCXR00_type*) 0xf0001b54u)	/* GPTA0 Local Timer Cell X Register 42  */
#define GPTA0_LTCXR43	(*(GPTA0_LTCXR00_type*) 0xf0001b5cu)	/* GPTA0 Local Timer Cell X Register 43  */
#define GPTA0_LTCXR44	(*(GPTA0_LTCXR00_type*) 0xf0001b64u)	/* GPTA0 Local Timer Cell X Register 44  */
#define GPTA0_LTCXR45	(*(GPTA0_LTCXR00_type*) 0xf0001b6cu)	/* GPTA0 Local Timer Cell X Register 45  */
#define GPTA0_LTCXR46	(*(GPTA0_LTCXR00_type*) 0xf0001b74u)	/* GPTA0 Local Timer Cell X Register 46  */
#define GPTA0_LTCXR47	(*(GPTA0_LTCXR00_type*) 0xf0001b7cu)	/* GPTA0 Local Timer Cell X Register 47  */
#define GPTA0_LTCXR48	(*(GPTA0_LTCXR00_type*) 0xf0001b84u)	/* GPTA0 Local Timer Cell X Register 48  */
#define GPTA0_LTCXR49	(*(GPTA0_LTCXR00_type*) 0xf0001b8cu)	/* GPTA0 Local Timer Cell X Register 49  */
#define GPTA0_LTCXR50	(*(GPTA0_LTCXR00_type*) 0xf0001b94u)	/* GPTA0 Local Timer Cell X Register 50  */
#define GPTA0_LTCXR51	(*(GPTA0_LTCXR00_type*) 0xf0001b9cu)	/* GPTA0 Local Timer Cell X Register 51  */
#define GPTA0_LTCXR52	(*(GPTA0_LTCXR00_type*) 0xf0001ba4u)	/* GPTA0 Local Timer Cell X Register 52  */
#define GPTA0_LTCXR53	(*(GPTA0_LTCXR00_type*) 0xf0001bacu)	/* GPTA0 Local Timer Cell X Register 53  */
#define GPTA0_LTCXR54	(*(GPTA0_LTCXR00_type*) 0xf0001bb4u)	/* GPTA0 Local Timer Cell X Register 54  */
#define GPTA0_LTCXR55	(*(GPTA0_LTCXR00_type*) 0xf0001bbcu)	/* GPTA0 Local Timer Cell X Register 55  */
#define GPTA0_LTCXR56	(*(GPTA0_LTCXR00_type*) 0xf0001bc4u)	/* GPTA0 Local Timer Cell X Register 56  */
#define GPTA0_LTCXR57	(*(GPTA0_LTCXR00_type*) 0xf0001bccu)	/* GPTA0 Local Timer Cell X Register 57  */
#define GPTA0_LTCXR58	(*(GPTA0_LTCXR00_type*) 0xf0001bd4u)	/* GPTA0 Local Timer Cell X Register 58  */
#define GPTA0_LTCXR59	(*(GPTA0_LTCXR00_type*) 0xf0001bdcu)	/* GPTA0 Local Timer Cell X Register 59  */
#define GPTA0_LTCXR60	(*(GPTA0_LTCXR00_type*) 0xf0001be4u)	/* GPTA0 Local Timer Cell X Register 60  */
#define GPTA0_LTCXR61	(*(GPTA0_LTCXR00_type*) 0xf0001becu)	/* GPTA0 Local Timer Cell X Register 61  */
#define GPTA0_LTCXR62	(*(GPTA0_LTCXR00_type*) 0xf0001bf4u)	/* GPTA0 Local Timer Cell X Register 62  */
#define LTCA2_LTCXR00	(*(GPTA0_LTCXR00_type*) 0xf0002a04u)	/* Local Timer Cell X Register 00  */
#define LTCA2_LTCXR01	(*(GPTA0_LTCXR00_type*) 0xf0002a0cu)	/* Local Timer Cell X Register 01  */
#define LTCA2_LTCXR02	(*(GPTA0_LTCXR00_type*) 0xf0002a14u)	/* Local Timer Cell X Register 02  */
#define LTCA2_LTCXR03	(*(GPTA0_LTCXR00_type*) 0xf0002a1cu)	/* Local Timer Cell X Register 03  */
#define LTCA2_LTCXR04	(*(GPTA0_LTCXR00_type*) 0xf0002a24u)	/* Local Timer Cell X Register 04  */
#define LTCA2_LTCXR05	(*(GPTA0_LTCXR00_type*) 0xf0002a2cu)	/* Local Timer Cell X Register 05  */
#define LTCA2_LTCXR06	(*(GPTA0_LTCXR00_type*) 0xf0002a34u)	/* Local Timer Cell X Register 06  */
#define LTCA2_LTCXR07	(*(GPTA0_LTCXR00_type*) 0xf0002a3cu)	/* Local Timer Cell X Register 07  */
#define LTCA2_LTCXR08	(*(GPTA0_LTCXR00_type*) 0xf0002a44u)	/* Local Timer Cell X Register 08  */
#define LTCA2_LTCXR09	(*(GPTA0_LTCXR00_type*) 0xf0002a4cu)	/* Local Timer Cell X Register 09  */
#define LTCA2_LTCXR10	(*(GPTA0_LTCXR00_type*) 0xf0002a54u)	/* Local Timer Cell X Register 10  */
#define LTCA2_LTCXR11	(*(GPTA0_LTCXR00_type*) 0xf0002a5cu)	/* Local Timer Cell X Register 11  */
#define LTCA2_LTCXR12	(*(GPTA0_LTCXR00_type*) 0xf0002a64u)	/* Local Timer Cell X Register 12  */
#define LTCA2_LTCXR13	(*(GPTA0_LTCXR00_type*) 0xf0002a6cu)	/* Local Timer Cell X Register 13  */
#define LTCA2_LTCXR14	(*(GPTA0_LTCXR00_type*) 0xf0002a74u)	/* Local Timer Cell X Register 14  */
#define LTCA2_LTCXR15	(*(GPTA0_LTCXR00_type*) 0xf0002a7cu)	/* Local Timer Cell X Register 15  */
#define LTCA2_LTCXR16	(*(GPTA0_LTCXR00_type*) 0xf0002a84u)	/* Local Timer Cell X Register 16  */
#define LTCA2_LTCXR17	(*(GPTA0_LTCXR00_type*) 0xf0002a8cu)	/* Local Timer Cell X Register 17  */
#define LTCA2_LTCXR18	(*(GPTA0_LTCXR00_type*) 0xf0002a94u)	/* Local Timer Cell X Register 18  */
#define LTCA2_LTCXR19	(*(GPTA0_LTCXR00_type*) 0xf0002a9cu)	/* Local Timer Cell X Register 19  */
#define LTCA2_LTCXR20	(*(GPTA0_LTCXR00_type*) 0xf0002aa4u)	/* Local Timer Cell X Register 20  */
#define LTCA2_LTCXR21	(*(GPTA0_LTCXR00_type*) 0xf0002aacu)	/* Local Timer Cell X Register 21  */
#define LTCA2_LTCXR22	(*(GPTA0_LTCXR00_type*) 0xf0002ab4u)	/* Local Timer Cell X Register 22  */
#define LTCA2_LTCXR23	(*(GPTA0_LTCXR00_type*) 0xf0002abcu)	/* Local Timer Cell X Register 23  */
#define LTCA2_LTCXR24	(*(GPTA0_LTCXR00_type*) 0xf0002ac4u)	/* Local Timer Cell X Register 24  */
#define LTCA2_LTCXR25	(*(GPTA0_LTCXR00_type*) 0xf0002accu)	/* Local Timer Cell X Register 25  */
#define LTCA2_LTCXR26	(*(GPTA0_LTCXR00_type*) 0xf0002ad4u)	/* Local Timer Cell X Register 26  */
#define LTCA2_LTCXR27	(*(GPTA0_LTCXR00_type*) 0xf0002adcu)	/* Local Timer Cell X Register 27  */
#define LTCA2_LTCXR28	(*(GPTA0_LTCXR00_type*) 0xf0002ae4u)	/* Local Timer Cell X Register 28  */
#define LTCA2_LTCXR29	(*(GPTA0_LTCXR00_type*) 0xf0002aecu)	/* Local Timer Cell X Register 29  */
#define LTCA2_LTCXR30	(*(GPTA0_LTCXR00_type*) 0xf0002af4u)	/* Local Timer Cell X Register 30  */

typedef volatile union
{
	struct
	{ 
		unsigned int X              : 16;
		unsigned int XS             : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_LTCXR63_type;
#define GPTA0_LTCXR63	(*(GPTA0_LTCXR63_type*) 0xf0001bfcu)	/* GPTA0 Local Timer Cell X Register 63  */
#define LTCA2_LTCXR31	(*(GPTA0_LTCXR63_type*) 0xf0002afcu)	/* Local Timer Cell X Register 31  */

typedef volatile union
{
	struct
	{ 
		unsigned int MUX0           : 2;
		unsigned int MUX1           : 2;
		unsigned int MUX2           : 2;
		unsigned int MUX3           : 2;
		unsigned int MUX4           : 2;
		unsigned int MUX5           : 2;
		unsigned int MUX6           : 2;
		unsigned int MUX7           : 2;
		unsigned int MUX8           : 2;
		unsigned int MUX9           : 2;
		unsigned int MUX10          : 2;
		unsigned int MUX11          : 2;
		unsigned int MUX12          : 2;
		unsigned int MUX13          : 2;
		unsigned int MUX14          : 2;
		unsigned int MUX15          : 2;
	} B;
	int I;
	unsigned int U;

} GPTA0_MMXCTR00_type;
#define GPTA0_MMXCTR00	(*(GPTA0_MMXCTR00_type*) 0xf0001f00u)	/* GPTA-to-MSC Multiplexer Control Register 00  */
#define GPTA0_MMXCTR01	(*(GPTA0_MMXCTR00_type*) 0xf0001f04u)	/* GPTA-to-MSC Multiplexer Control Register 01  */

typedef volatile union
{
	struct
	{ 
		unsigned int MAEN           : 1;
		unsigned int WCRES          : 1;
		/* const */ unsigned int FIFOFULL       : 1;
		unsigned int                : 5;
		/* const */ unsigned int FIFOFILLCNT    : 6;
		unsigned int                : 18;
	} B;
	int I;
	unsigned int U;

} GPTA0_MRACTL_type;
#define GPTA0_MRACTL	(*(GPTA0_MRACTL_type*) 0xf0001838u)	/* GPTA0 Multiplexer Register Array Control Register  */
#define LTCA2_MRACTL	(*(GPTA0_MRACTL_type*) 0xf0002838u)	/* Multiplexer Register Array Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 DATAIN         : 32;
	} B;
	int I;
	unsigned int U;

} GPTA0_MRADIN_type;
#define GPTA0_MRADIN	(*(GPTA0_MRADIN_type*) 0xf000183cu)	/* GPTA0 Multiplexer Register Array Data In Register  */
#define LTCA2_MRADIN	(*(GPTA0_MRADIN_type*) 0xf000283cu)	/* Multiplexer Register Array Data In Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 DATAOUT        : 32;
	} B;
	int I;
	unsigned int U;

} GPTA0_MRADOUT_type;
#define GPTA0_MRADOUT	(*(GPTA0_MRADOUT_type*) 0xf0001840u)	/* GPTA0 Multiplexer Register Array Data Out Register  */
#define LTCA2_MRADOUT	(*(GPTA0_MRADOUT_type*) 0xf0002840u)	/* Multiplexer Register Array Data Out Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MUX0           : 1;
		unsigned int TSE0           : 1;
		unsigned int ERR0           : 1;
		unsigned int                : 1;
		unsigned int MUX1           : 1;
		unsigned int TSE1           : 1;
		unsigned int ERR1           : 1;
		unsigned int                : 25;
	} B;
	int I;
	unsigned int U;

} GPTA0_PDLCTR_type;
#define GPTA0_PDLCTR	(*(GPTA0_PDLCTR_type*) 0xf0001878u)	/* GPTA0 Phase Discrimination Logic Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CNT            : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_PLLCNT_type;
#define GPTA0_PLLCNT	(*(GPTA0_PLLCNT_type*) 0xf00018c8u)	/* GPTA0 Phase Locked Loop Counter Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MUX            : 2;
		unsigned int AEN            : 1;
		unsigned int PEN            : 1;
		unsigned int REN            : 1;
		unsigned int                : 27;
	} B;
	int I;
	unsigned int U;

} GPTA0_PLLCTR_type;
#define GPTA0_PLLCTR	(*(GPTA0_PLLCTR_type*) 0xf00018c0u)	/* GPTA0 Phase Locked Loop Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DTR            : 25;
		unsigned int                : 7;
	} B;
	int I;
	unsigned int U;

} GPTA0_PLLDTR_type;
#define GPTA0_PLLDTR	(*(GPTA0_PLLDTR_type*) 0xf00018d4u)	/* GPTA0 Phase Locked Loop Delta Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int MTI            : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_PLLMTI_type;
#define GPTA0_PLLMTI	(*(GPTA0_PLLMTI_type*) 0xf00018c4u)	/* GPTA0 Phase Locked Loop Microtick Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STP            : 16;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_PLLSTP_type;
#define GPTA0_PLLSTP	(*(GPTA0_PLLSTP_type*) 0xf00018ccu)	/* GPTA0 Phase Locked Loop Step Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_SRC00_type;
#define GPTA0_SRC00	(*(GPTA0_SRC00_type*) 0xf0001ffcu)	/* GPTA0 Interrupt Service Request Control Register 00  */
#define GPTA0_SRC01	(*(GPTA0_SRC00_type*) 0xf0001ff8u)	/* GPTA0 Interrupt Service Request Control Register 01  */
#define GPTA0_SRC02	(*(GPTA0_SRC00_type*) 0xf0001ff4u)	/* GPTA0 Interrupt Service Request Control Register 02  */
#define GPTA0_SRC03	(*(GPTA0_SRC00_type*) 0xf0001ff0u)	/* GPTA0 Interrupt Service Request Control Register 03  */
#define GPTA0_SRC04	(*(GPTA0_SRC00_type*) 0xf0001fecu)	/* GPTA0 Interrupt Service Request Control Register 04  */
#define GPTA0_SRC05	(*(GPTA0_SRC00_type*) 0xf0001fe8u)	/* GPTA0 Interrupt Service Request Control Register 05  */
#define GPTA0_SRC06	(*(GPTA0_SRC00_type*) 0xf0001fe4u)	/* GPTA0 Interrupt Service Request Control Register 06  */
#define GPTA0_SRC07	(*(GPTA0_SRC00_type*) 0xf0001fe0u)	/* GPTA0 Interrupt Service Request Control Register 07  */
#define GPTA0_SRC08	(*(GPTA0_SRC00_type*) 0xf0001fdcu)	/* GPTA0 Interrupt Service Request Control Register 08  */
#define GPTA0_SRC09	(*(GPTA0_SRC00_type*) 0xf0001fd8u)	/* GPTA0 Interrupt Service Request Control Register 09  */
#define GPTA0_SRC10	(*(GPTA0_SRC00_type*) 0xf0001fd4u)	/* GPTA0 Interrupt Service Request Control Register 10  */
#define GPTA0_SRC11	(*(GPTA0_SRC00_type*) 0xf0001fd0u)	/* GPTA0 Interrupt Service Request Control Register 11  */
#define GPTA0_SRC12	(*(GPTA0_SRC00_type*) 0xf0001fccu)	/* GPTA0 Interrupt Service Request Control Register 12  */
#define GPTA0_SRC13	(*(GPTA0_SRC00_type*) 0xf0001fc8u)	/* GPTA0 Interrupt Service Request Control Register 13  */
#define GPTA0_SRC14	(*(GPTA0_SRC00_type*) 0xf0001fc4u)	/* GPTA0 Interrupt Service Request Control Register 14  */
#define GPTA0_SRC15	(*(GPTA0_SRC00_type*) 0xf0001fc0u)	/* GPTA0 Interrupt Service Request Control Register 15  */
#define GPTA0_SRC16	(*(GPTA0_SRC00_type*) 0xf0001fbcu)	/* GPTA0 Interrupt Service Request Control Register 16  */
#define GPTA0_SRC17	(*(GPTA0_SRC00_type*) 0xf0001fb8u)	/* GPTA0 Interrupt Service Request Control Register 17  */
#define GPTA0_SRC18	(*(GPTA0_SRC00_type*) 0xf0001fb4u)	/* GPTA0 Interrupt Service Request Control Register 18  */
#define GPTA0_SRC19	(*(GPTA0_SRC00_type*) 0xf0001fb0u)	/* GPTA0 Interrupt Service Request Control Register 19  */
#define GPTA0_SRC20	(*(GPTA0_SRC00_type*) 0xf0001facu)	/* GPTA0 Interrupt Service Request Control Register 20  */
#define GPTA0_SRC21	(*(GPTA0_SRC00_type*) 0xf0001fa8u)	/* GPTA0 Interrupt Service Request Control Register 21  */
#define GPTA0_SRC22	(*(GPTA0_SRC00_type*) 0xf0001fa4u)	/* GPTA0 Interrupt Service Request Control Register 22  */
#define GPTA0_SRC23	(*(GPTA0_SRC00_type*) 0xf0001fa0u)	/* GPTA0 Interrupt Service Request Control Register 23  */
#define GPTA0_SRC24	(*(GPTA0_SRC00_type*) 0xf0001f9cu)	/* GPTA0 Interrupt Service Request Control Register 24  */
#define GPTA0_SRC25	(*(GPTA0_SRC00_type*) 0xf0001f98u)	/* GPTA0 Interrupt Service Request Control Register 25  */
#define GPTA0_SRC26	(*(GPTA0_SRC00_type*) 0xf0001f94u)	/* GPTA0 Interrupt Service Request Control Register 26  */
#define GPTA0_SRC27	(*(GPTA0_SRC00_type*) 0xf0001f90u)	/* GPTA0 Interrupt Service Request Control Register 27  */
#define GPTA0_SRC28	(*(GPTA0_SRC00_type*) 0xf0001f8cu)	/* GPTA0 Interrupt Service Request Control Register 28  */
#define GPTA0_SRC29	(*(GPTA0_SRC00_type*) 0xf0001f88u)	/* GPTA0 Interrupt Service Request Control Register 29  */
#define GPTA0_SRC30	(*(GPTA0_SRC00_type*) 0xf0001f84u)	/* GPTA0 Interrupt Service Request Control Register 30  */
#define GPTA0_SRC31	(*(GPTA0_SRC00_type*) 0xf0001f80u)	/* GPTA0 Interrupt Service Request Control Register 31  */
#define GPTA0_SRC32	(*(GPTA0_SRC00_type*) 0xf0001f7cu)	/* GPTA0 Interrupt Service Request Control Register 32  */
#define GPTA0_SRC33	(*(GPTA0_SRC00_type*) 0xf0001f78u)	/* GPTA0 Interrupt Service Request Control Register 33  */
#define GPTA0_SRC34	(*(GPTA0_SRC00_type*) 0xf0001f74u)	/* GPTA0 Interrupt Service Request Control Register 34  */
#define GPTA0_SRC35	(*(GPTA0_SRC00_type*) 0xf0001f70u)	/* GPTA0 Interrupt Service Request Control Register 35  */
#define GPTA0_SRC36	(*(GPTA0_SRC00_type*) 0xf0001f6cu)	/* GPTA0 Interrupt Service Request Control Register 36  */
#define GPTA0_SRC37	(*(GPTA0_SRC00_type*) 0xf0001f68u)	/* GPTA0 Interrupt Service Request Control Register 37  */
#define LTCA2_SRC00	(*(GPTA0_SRC00_type*) 0xf0002ffcu)	/* LTCA2 Interrupt Service Request Control Register 00  */
#define LTCA2_SRC01	(*(GPTA0_SRC00_type*) 0xf0002ff8u)	/* LTCA2 Interrupt Service Request Control Register 01  */
#define LTCA2_SRC02	(*(GPTA0_SRC00_type*) 0xf0002ff4u)	/* LTCA2 Interrupt Service Request Control Register 02  */
#define LTCA2_SRC03	(*(GPTA0_SRC00_type*) 0xf0002ff0u)	/* LTCA2 Interrupt Service Request Control Register 03  */
#define LTCA2_SRC04	(*(GPTA0_SRC00_type*) 0xf0002fecu)	/* LTCA2 Interrupt Service Request Control Register 04  */
#define LTCA2_SRC05	(*(GPTA0_SRC00_type*) 0xf0002fe8u)	/* LTCA2 Interrupt Service Request Control Register 05  */
#define LTCA2_SRC06	(*(GPTA0_SRC00_type*) 0xf0002fe4u)	/* LTCA2 Interrupt Service Request Control Register 06  */
#define LTCA2_SRC07	(*(GPTA0_SRC00_type*) 0xf0002fe0u)	/* LTCA2 Interrupt Service Request Control Register 07  */

typedef volatile union
{
	struct
	{ 
		unsigned int GTC01R         : 1;
		unsigned int GTC03R         : 1;
		unsigned int GTC05R         : 1;
		unsigned int GTC07R         : 1;
		unsigned int GTC09R         : 1;
		unsigned int GTC11R         : 1;
		unsigned int GTC13R         : 1;
		unsigned int GTC15R         : 1;
		unsigned int GTC17R         : 1;
		unsigned int GTC19R         : 1;
		unsigned int GTC21R         : 1;
		unsigned int GTC23R         : 1;
		unsigned int GTC25R         : 1;
		unsigned int GTC27R         : 1;
		unsigned int GTC29R         : 1;
		unsigned int GTC31R         : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} GPTA0_SRNR_type;
#define GPTA0_SRNR	(*(GPTA0_SRNR_type*) 0xf0001830u)	/* GPTA0 Service Request Node Redirection Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DCM00R         : 1;
		unsigned int DCM00F         : 1;
		unsigned int DCM00C         : 1;
		unsigned int DCM01R         : 1;
		unsigned int DCM01F         : 1;
		unsigned int DCM01C         : 1;
		unsigned int DCM02R         : 1;
		unsigned int DCM02F         : 1;
		unsigned int DCM02C         : 1;
		unsigned int DCM03R         : 1;
		unsigned int DCM03F         : 1;
		unsigned int DCM03C         : 1;
		unsigned int PLL            : 1;
		unsigned int GT00           : 1;
		unsigned int GT01           : 1;
		unsigned int                : 17;
	} B;
	int I;
	unsigned int U;

} GPTA0_SRSC0_type;
#define GPTA0_SRSC0	(*(GPTA0_SRSC0_type*) 0xf0001810u)	/* GPTA0 Service Request State Clear Register 0  */
#define GPTA0_SRSS0	(*(GPTA0_SRSC0_type*) 0xf0001814u)	/* GPTA0 Service Request State Set Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int GTC0           : 1;
		unsigned int GTC1           : 1;
		unsigned int GTC2           : 1;
		unsigned int GTC3           : 1;
		unsigned int GTC4           : 1;
		unsigned int GTC5           : 1;
		unsigned int GTC6           : 1;
		unsigned int GTC7           : 1;
		unsigned int GTC8           : 1;
		unsigned int GTC9           : 1;
		unsigned int GTC10          : 1;
		unsigned int GTC11          : 1;
		unsigned int GTC12          : 1;
		unsigned int GTC13          : 1;
		unsigned int GTC14          : 1;
		unsigned int GTC15          : 1;
		unsigned int GTC16          : 1;
		unsigned int GTC17          : 1;
		unsigned int GTC18          : 1;
		unsigned int GTC19          : 1;
		unsigned int GTC20          : 1;
		unsigned int GTC21          : 1;
		unsigned int GTC22          : 1;
		unsigned int GTC23          : 1;
		unsigned int GTC24          : 1;
		unsigned int GTC25          : 1;
		unsigned int GTC26          : 1;
		unsigned int GTC27          : 1;
		unsigned int GTC28          : 1;
		unsigned int GTC29          : 1;
		unsigned int GTC30          : 1;
		unsigned int GTC31          : 1;
	} B;
	int I;
	unsigned int U;

} GPTA0_SRSC1_type;
#define GPTA0_SRSC1	(*(GPTA0_SRSC1_type*) 0xf0001818u)	/* GPTA0 Service Request State Clear Register 1  */
#define GPTA0_SRSS1	(*(GPTA0_SRSC1_type*) 0xf000181cu)	/* GPTA0 Service Request State Set Register 1  */

typedef volatile union
{
	struct
	{ 
		unsigned int LTC0           : 1;
		unsigned int LTC1           : 1;
		unsigned int LTC2           : 1;
		unsigned int LTC3           : 1;
		unsigned int LTC4           : 1;
		unsigned int LTC5           : 1;
		unsigned int LTC6           : 1;
		unsigned int LTC7           : 1;
		unsigned int LTC8           : 1;
		unsigned int LTC9           : 1;
		unsigned int LTC10          : 1;
		unsigned int LTC11          : 1;
		unsigned int LTC12          : 1;
		unsigned int LTC13          : 1;
		unsigned int LTC14          : 1;
		unsigned int LTC15          : 1;
		unsigned int LTC16          : 1;
		unsigned int LTC17          : 1;
		unsigned int LTC18          : 1;
		unsigned int LTC19          : 1;
		unsigned int LTC20          : 1;
		unsigned int LTC21          : 1;
		unsigned int LTC22          : 1;
		unsigned int LTC23          : 1;
		unsigned int LTC24          : 1;
		unsigned int LTC25          : 1;
		unsigned int LTC26          : 1;
		unsigned int LTC27          : 1;
		unsigned int LTC28          : 1;
		unsigned int LTC29          : 1;
		unsigned int LTC30          : 1;
		unsigned int LTC31          : 1;
	} B;
	int I;
	unsigned int U;

} GPTA0_SRSC2_type;
#define GPTA0_SRSC2	(*(GPTA0_SRSC2_type*) 0xf0001820u)	/* GPTA0 Service Request State Clear Register 2  */
#define GPTA0_SRSS2	(*(GPTA0_SRSC2_type*) 0xf0001824u)	/* GPTA0 Service Request State Set Register 2  */
#define LTCA2_SRSC2	(*(GPTA0_SRSC2_type*) 0xf0002820u)	/* LTCA2 Service Request State Clear Register 2  */
#define LTCA2_SRSS2	(*(GPTA0_SRSC2_type*) 0xf0002824u)	/* LTCA2 Service Request State Set Register 2  */

typedef volatile union
{
	struct
	{ 
		unsigned int LTC32          : 1;
		unsigned int LTC33          : 1;
		unsigned int LTC34          : 1;
		unsigned int LTC35          : 1;
		unsigned int LTC36          : 1;
		unsigned int LTC37          : 1;
		unsigned int LTC38          : 1;
		unsigned int LTC39          : 1;
		unsigned int LTC40          : 1;
		unsigned int LTC41          : 1;
		unsigned int LTC42          : 1;
		unsigned int LTC43          : 1;
		unsigned int LTC44          : 1;
		unsigned int LTC45          : 1;
		unsigned int LTC46          : 1;
		unsigned int LTC47          : 1;
		unsigned int LTC48          : 1;
		unsigned int LTC49          : 1;
		unsigned int LTC50          : 1;
		unsigned int LTC51          : 1;
		unsigned int LTC52          : 1;
		unsigned int LTC53          : 1;
		unsigned int LTC54          : 1;
		unsigned int LTC55          : 1;
		unsigned int LTC56          : 1;
		unsigned int LTC57          : 1;
		unsigned int LTC58          : 1;
		unsigned int LTC59          : 1;
		unsigned int LTC60          : 1;
		unsigned int LTC61          : 1;
		unsigned int LTC62          : 1;
		unsigned int LTC63          : 1;
	} B;
	int I;
	unsigned int U;

} GPTA0_SRSC3_type;
#define GPTA0_SRSC3	(*(GPTA0_SRSC3_type*) 0xf0001828u)	/* GPTA0 Service Request State Clear Register 3  */
#define GPTA0_SRSS3	(*(GPTA0_SRSC3_type*) 0xf000182cu)	/* GPTA0 Service Request State Set Register 3  */


/* ADC */
typedef volatile union
{
	struct
	{ 
		unsigned int ALIAS0         : 4;
		unsigned int                : 4;
		unsigned int ALIAS1         : 4;
		unsigned int                : 20;
	} B;
	int I;
	unsigned int U;

} ADC0_ALR0_type;
#define ADC0_ALR0	(*(ADC0_ALR0_type*) 0xf0101210u)	/* Alias Register 0  */
#define ADC1_ALR0	(*(ADC0_ALR0_type*) 0xf0101610u)	/* Alias Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int RG0            : 1;
		unsigned int RG1            : 1;
		unsigned int RG2            : 1;
		unsigned int RG3            : 1;
		unsigned int RG4            : 1;
		unsigned int RG5            : 1;
		unsigned int                : 9;
		unsigned int ACCERR         : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_APR_type;
#define ADC0_APR	(*(ADC0_APR_type*) 0xf0101218u)	/* Access Protection Register  */
#define ADC1_APR	(*(ADC0_APR_type*) 0xf0101618u)	/* Access Protection Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ASEN0          : 1;
		unsigned int ASEN1          : 1;
		unsigned int ASEN2          : 1;
		unsigned int ASEN3          : 1;
		unsigned int ASEN4          : 1;
		unsigned int                : 27;
	} B;
	int I;
	unsigned int U;

} ADC0_ASENR_type;
#define ADC0_ASENR	(*(ADC0_ASENR_type*) 0xf010103cu)	/* Arbitration Slot Enable Register  */
#define ADC1_ASENR	(*(ADC0_ASENR_type*) 0xf010143cu)	/* Arbitration Slot Enable Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int BNDASEL        : 2;
		unsigned int BNDBSEL        : 2;
		unsigned int LCC            : 3;
		unsigned int SYNC           : 1;
		unsigned int REFSEL         : 2;
		unsigned int ICLSEL         : 2;
		unsigned int RESRSEL        : 4;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_CHCTR0_type;
#define ADC0_CHCTR0	(*(ADC0_CHCTR0_type*) 0xf0101100u)	/* Channel 0 Control Register  */
#define ADC0_CHCTR1	(*(ADC0_CHCTR0_type*) 0xf0101104u)	/* Channel 1 Control Register  */
#define ADC0_CHCTR10	(*(ADC0_CHCTR0_type*) 0xf0101128u)	/* Channel 10 Control Register  */
#define ADC0_CHCTR11	(*(ADC0_CHCTR0_type*) 0xf010112cu)	/* Channel 11 Control Register  */
#define ADC0_CHCTR12	(*(ADC0_CHCTR0_type*) 0xf0101130u)	/* Channel 12 Control Register  */
#define ADC0_CHCTR13	(*(ADC0_CHCTR0_type*) 0xf0101134u)	/* Channel 13 Control Register  */
#define ADC0_CHCTR14	(*(ADC0_CHCTR0_type*) 0xf0101138u)	/* Channel 14 Control Register  */
#define ADC0_CHCTR15	(*(ADC0_CHCTR0_type*) 0xf010113cu)	/* Channel 15 Control Register  */
#define ADC0_CHCTR2	(*(ADC0_CHCTR0_type*) 0xf0101108u)	/* Channel 2 Control Register  */
#define ADC0_CHCTR3	(*(ADC0_CHCTR0_type*) 0xf010110cu)	/* Channel 3 Control Register  */
#define ADC0_CHCTR4	(*(ADC0_CHCTR0_type*) 0xf0101110u)	/* Channel 4 Control Register  */
#define ADC0_CHCTR5	(*(ADC0_CHCTR0_type*) 0xf0101114u)	/* Channel 5 Control Register  */
#define ADC0_CHCTR6	(*(ADC0_CHCTR0_type*) 0xf0101118u)	/* Channel 6 Control Register  */
#define ADC0_CHCTR7	(*(ADC0_CHCTR0_type*) 0xf010111cu)	/* Channel 7 Control Register  */
#define ADC0_CHCTR8	(*(ADC0_CHCTR0_type*) 0xf0101120u)	/* Channel 8 Control Register  */
#define ADC0_CHCTR9	(*(ADC0_CHCTR0_type*) 0xf0101124u)	/* Channel 9 Control Register  */
#define ADC1_CHCTR0	(*(ADC0_CHCTR0_type*) 0xf0101500u)	/* Channel 0 Control Register  */
#define ADC1_CHCTR1	(*(ADC0_CHCTR0_type*) 0xf0101504u)	/* Channel 1 Control Register  */
#define ADC1_CHCTR10	(*(ADC0_CHCTR0_type*) 0xf0101528u)	/* Channel 10 Control Register  */
#define ADC1_CHCTR11	(*(ADC0_CHCTR0_type*) 0xf010152cu)	/* Channel 11 Control Register  */
#define ADC1_CHCTR12	(*(ADC0_CHCTR0_type*) 0xf0101530u)	/* Channel 12 Control Register  */
#define ADC1_CHCTR13	(*(ADC0_CHCTR0_type*) 0xf0101534u)	/* Channel 13 Control Register  */
#define ADC1_CHCTR14	(*(ADC0_CHCTR0_type*) 0xf0101538u)	/* Channel 14 Control Register  */
#define ADC1_CHCTR15	(*(ADC0_CHCTR0_type*) 0xf010153cu)	/* Channel 15 Control Register  */
#define ADC1_CHCTR2	(*(ADC0_CHCTR0_type*) 0xf0101508u)	/* Channel 2 Control Register  */
#define ADC1_CHCTR3	(*(ADC0_CHCTR0_type*) 0xf010150cu)	/* Channel 3 Control Register  */
#define ADC1_CHCTR4	(*(ADC0_CHCTR0_type*) 0xf0101510u)	/* Channel 4 Control Register  */
#define ADC1_CHCTR5	(*(ADC0_CHCTR0_type*) 0xf0101514u)	/* Channel 5 Control Register  */
#define ADC1_CHCTR6	(*(ADC0_CHCTR0_type*) 0xf0101518u)	/* Channel 6 Control Register  */
#define ADC1_CHCTR7	(*(ADC0_CHCTR0_type*) 0xf010151cu)	/* Channel 7 Control Register  */
#define ADC1_CHCTR8	(*(ADC0_CHCTR0_type*) 0xf0101520u)	/* Channel 8 Control Register  */
#define ADC1_CHCTR9	(*(ADC0_CHCTR0_type*) 0xf0101524u)	/* Channel 9 Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CHENP0         : 3;
		unsigned int                : 1;
		unsigned int CHENP1         : 3;
		unsigned int                : 1;
		unsigned int CHENP2         : 3;
		unsigned int                : 1;
		unsigned int CHENP3         : 3;
		unsigned int                : 1;
		unsigned int CHENP4         : 3;
		unsigned int                : 1;
		unsigned int CHENP5         : 3;
		unsigned int                : 1;
		unsigned int CHENP6         : 3;
		unsigned int                : 1;
		unsigned int CHENP7         : 3;
		unsigned int                : 1;
	} B;
	int I;
	unsigned int U;

} ADC0_CHENPR0_type;
#define ADC0_CHENPR0	(*(ADC0_CHENPR0_type*) 0xf0101068u)	/* Channel Event Node Pointer Register 0  */
#define ADC1_CHENPR0	(*(ADC0_CHENPR0_type*) 0xf0101468u)	/* Channel Event Node Pointer Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int CHENP8         : 3;
		unsigned int                : 1;
		unsigned int CHENP9         : 3;
		unsigned int                : 1;
		unsigned int CHENP10        : 3;
		unsigned int                : 1;
		unsigned int CHENP11        : 3;
		unsigned int                : 1;
		unsigned int CHENP12        : 3;
		unsigned int                : 1;
		unsigned int CHENP13        : 3;
		unsigned int                : 1;
		unsigned int CHENP14        : 3;
		unsigned int                : 1;
		unsigned int CHENP15        : 3;
		unsigned int                : 1;
	} B;
	int I;
	unsigned int U;

} ADC0_CHENPR8_type;
#define ADC0_CHENPR8	(*(ADC0_CHENPR8_type*) 0xf010106cu)	/* Channel Event Node Pointer Register 8  */
#define ADC1_CHENPR8	(*(ADC0_CHENPR8_type*) 0xf010146cu)	/* Channel Event Node Pointer Register 8  */

typedef volatile union
{
	struct
	{ 
		unsigned int CFC0           : 1;
		unsigned int CFC1           : 1;
		unsigned int CFC2           : 1;
		unsigned int CFC3           : 1;
		unsigned int CFC4           : 1;
		unsigned int CFC5           : 1;
		unsigned int CFC6           : 1;
		unsigned int CFC7           : 1;
		unsigned int CFC8           : 1;
		unsigned int CFC9           : 1;
		unsigned int CFC10          : 1;
		unsigned int CFC11          : 1;
		unsigned int CFC12          : 1;
		unsigned int CFC13          : 1;
		unsigned int CFC14          : 1;
		unsigned int CFC15          : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_CHFCR_type;
#define ADC0_CHFCR	(*(ADC0_CHFCR_type*) 0xf0101064u)	/* Channel Flag Clear Register  */
#define ADC1_CHFCR	(*(ADC0_CHFCR_type*) 0xf0101464u)	/* Channel Flag Clear Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int FC0            : 1;
		unsigned int FC1            : 1;
		unsigned int FC2            : 1;
		unsigned int FC3            : 1;
		unsigned int FC4            : 1;
		unsigned int FC5            : 1;
		unsigned int FC6            : 1;
		unsigned int FC7            : 1;
		unsigned int FC8            : 1;
		unsigned int FC9            : 1;
		unsigned int FC10           : 1;
		unsigned int FC11           : 1;
		unsigned int FC12           : 1;
		unsigned int FC13           : 1;
		unsigned int FC14           : 1;
		unsigned int FC15           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_CHFR_type;
#define ADC0_CHFR	(*(ADC0_CHFR_type*) 0xf0101060u)	/* Channel Flag Register  */
#define ADC1_CHFR	(*(ADC0_CHFR_type*) 0xf0101460u)	/* Channel Flag Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} ADC0_CLC_type;
#define ADC0_CLC	(*(ADC0_CLC_type*) 0xf0101000u)	/* ADC Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CH0            : 1;
		unsigned int CH1            : 1;
		unsigned int CH2            : 1;
		unsigned int CH3            : 1;
		unsigned int CH4            : 1;
		unsigned int CH5            : 1;
		unsigned int CH6            : 1;
		unsigned int CH7            : 1;
		unsigned int CH8            : 1;
		unsigned int CH9            : 1;
		unsigned int CH10           : 1;
		unsigned int CH11           : 1;
		unsigned int CH12           : 1;
		unsigned int CH13           : 1;
		unsigned int CH14           : 1;
		unsigned int CH15           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_CRCR1_type;
#define ADC0_CRCR1	(*(ADC0_CRCR1_type*) 0xf0101090u)	/* Conversion Request 1 Control Register  */
#define ADC0_CRCR3	(*(ADC0_CRCR1_type*) 0xf01010b0u)	/* Conversion Request 3 Control Register  */
#define ADC1_CRCR1	(*(ADC0_CRCR1_type*) 0xf0101490u)	/* Conversion Request 1 Control Register  */
#define ADC1_CRCR3	(*(ADC0_CRCR1_type*) 0xf01014b0u)	/* Conversion Request 3 Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ENGT           : 2;
		unsigned int ENTR           : 1;
		unsigned int ENSI           : 1;
		unsigned int SCAN           : 1;
		unsigned int LDM            : 1;
		unsigned int                : 1;
		/* const */ unsigned int REQGT          : 1;
		unsigned int CLRPND         : 1;
		unsigned int LDEV           : 1;
		unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} ADC0_CRMR1_type;
#define ADC0_CRMR1	(*(ADC0_CRMR1_type*) 0xf0101098u)	/* Conversion Request 1 Mode Register  */
#define ADC0_CRMR3	(*(ADC0_CRMR1_type*) 0xf01010b8u)	/* Conversion Request 3 Mode Register  */
#define ADC1_CRMR1	(*(ADC0_CRMR1_type*) 0xf0101498u)	/* Conversion Request 1 Mode Register  */
#define ADC1_CRMR3	(*(ADC0_CRMR1_type*) 0xf01014b8u)	/* Conversion Request 3 Mode Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CHP0           : 1;
		unsigned int CHP1           : 1;
		unsigned int CHP2           : 1;
		unsigned int CHP3           : 1;
		unsigned int CHP4           : 1;
		unsigned int CHP5           : 1;
		unsigned int CHP6           : 1;
		unsigned int CHP7           : 1;
		unsigned int CHP8           : 1;
		unsigned int CHP9           : 1;
		unsigned int CHP10          : 1;
		unsigned int CHP11          : 1;
		unsigned int CHP12          : 1;
		unsigned int CHP13          : 1;
		unsigned int CHP14          : 1;
		unsigned int CHP15          : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_CRPR1_type;
#define ADC0_CRPR1	(*(ADC0_CRPR1_type*) 0xf0101094u)	/* Conversion Request 1 Pending Register  */
#define ADC0_CRPR3	(*(ADC0_CRPR1_type*) 0xf01010b4u)	/* Conversion Request 3 Pending Register  */
#define ADC1_CRPR1	(*(ADC0_CRPR1_type*) 0xf0101494u)	/* Conversion Request 1 Pending Register  */
#define ADC1_CRPR3	(*(ADC0_CRPR1_type*) 0xf01014b4u)	/* Conversion Request 3 Pending Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SETEMUX        : 3;
		unsigned int                : 1;
		/* const */ unsigned int EMUX           : 3;
		unsigned int                : 1;
		unsigned int EMSAMPLE       : 8;
		unsigned int EMUXCHNR       : 4;
		unsigned int                : 1;
		unsigned int TROEN          : 1;
		unsigned int SCANEN         : 1;
		unsigned int EMUXEN         : 1;
		unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} ADC0_EMCTR_type;
#define ADC0_EMCTR	(*(ADC0_EMCTR_type*) 0xf0101220u)	/* External Multiplexer Control Register  */
#define ADC1_EMCTR	(*(ADC0_EMCTR_type*) 0xf0101620u)	/* External Multiplexer Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int CFR0           : 1;
		unsigned int CFR1           : 1;
		unsigned int CFR2           : 1;
		unsigned int CFR3           : 1;
		unsigned int CFR4           : 1;
		unsigned int CFR5           : 1;
		unsigned int CFR6           : 1;
		unsigned int CFR7           : 1;
		unsigned int CFR8           : 1;
		unsigned int CFR9           : 1;
		unsigned int CFR10          : 1;
		unsigned int CFR11          : 1;
		unsigned int CFR12          : 1;
		unsigned int CFR13          : 1;
		unsigned int CFR14          : 1;
		unsigned int CFR15          : 1;
		unsigned int CFS0           : 1;
		unsigned int CFS1           : 1;
		unsigned int CFS2           : 1;
		unsigned int CFS3           : 1;
		unsigned int CFS4           : 1;
		unsigned int                : 11;
	} B;
	int I;
	unsigned int U;

} ADC0_EVFCR_type;
#define ADC0_EVFCR	(*(ADC0_EVFCR_type*) 0xf0101074u)	/* Event Flag Clear Register  */
#define ADC1_EVFCR	(*(ADC0_EVFCR_type*) 0xf0101474u)	/* Event Flag Clear Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int FR0            : 1;
		unsigned int FR1            : 1;
		unsigned int FR2            : 1;
		unsigned int FR3            : 1;
		unsigned int FR4            : 1;
		unsigned int FR5            : 1;
		unsigned int FR6            : 1;
		unsigned int FR7            : 1;
		unsigned int FR8            : 1;
		unsigned int FR9            : 1;
		unsigned int FR10           : 1;
		unsigned int FR11           : 1;
		unsigned int FR12           : 1;
		unsigned int FR13           : 1;
		unsigned int FR14           : 1;
		unsigned int FR15           : 1;
		unsigned int FS0            : 1;
		unsigned int FS1            : 1;
		unsigned int FS2            : 1;
		unsigned int FS3            : 1;
		unsigned int FS4            : 1;
		unsigned int                : 3;
		/* const */ unsigned int GFS0           : 1;
		/* const */ unsigned int GFS1           : 1;
		/* const */ unsigned int GFS2           : 1;
		/* const */ unsigned int GFS3           : 1;
		/* const */ unsigned int GFS4           : 1;
		unsigned int                : 3;
	} B;
	int I;
	unsigned int U;

} ADC0_EVFR_type;
#define ADC0_EVFR	(*(ADC0_EVFR_type*) 0xf0101070u)	/* Event Flag Register  */
#define ADC1_EVFR	(*(ADC0_EVFR_type*) 0xf0101470u)	/* Event Flag Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SENP0          : 3;
		unsigned int                : 1;
		unsigned int SENP1          : 3;
		unsigned int                : 1;
		unsigned int SENP2          : 3;
		unsigned int                : 1;
		unsigned int SENP3          : 3;
		unsigned int                : 1;
		unsigned int SENP4          : 3;
		unsigned int                : 13;
	} B;
	int I;
	unsigned int U;

} ADC0_EVNPR_type;
#define ADC0_EVNPR	(*(ADC0_EVNPR_type*) 0xf0101078u)	/* Event Node Pointer Register  */
#define ADC1_EVNPR	(*(ADC0_EVNPR_type*) 0xf0101478u)	/* Event Node Pointer Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 4;
		unsigned int MTM7           : 1;
		unsigned int SUCAL          : 1;
		unsigned int DPCAL          : 1;
		unsigned int                : 25;
	} B;
	int I;
	unsigned int U;

} ADC0_GLOBCFG_type;
#define ADC0_GLOBCFG	(*(ADC0_GLOBCFG_type*) 0xf0101034u)	/* Global Configuration Register  */
#define ADC1_GLOBCFG	(*(ADC0_GLOBCFG_type*) 0xf0101434u)	/* Global Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DIVA           : 6;
		unsigned int DIVD           : 2;
		unsigned int ANON           : 2;
		unsigned int ARBRND         : 2;
		unsigned int                : 3;
		unsigned int ARBM           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_GLOBCTR_type;
#define ADC0_GLOBCTR	(*(ADC0_GLOBCTR_type*) 0xf0101030u)	/* Global Control Register  */
#define ADC1_GLOBCTR	(*(ADC0_GLOBCTR_type*) 0xf0101430u)	/* Global Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int BUSY           : 1;
		/* const */ unsigned int SAMPLE         : 1;
		/* const */ unsigned int CAL            : 1;
		/* const */ unsigned int CHNR           : 4;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int ANON           : 2;
		/* const */ unsigned int SYNRUN         : 1;
		/* const */ unsigned int CSRC           : 3;
		/* const */ unsigned int                : 18;
	} B;
	int I;
	unsigned int U;

} ADC0_GLOBSTR_type;
#define ADC0_GLOBSTR	(*(ADC0_GLOBSTR_type*) 0xf0101038u)	/* Global Status Register  */
#define ADC1_GLOBSTR	(*(ADC0_GLOBSTR_type*) 0xf0101438u)	/* Global Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STC            : 8;
		unsigned int DW             : 2;
		unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} ADC0_INPCR0_type;
#define ADC0_INPCR0	(*(ADC0_INPCR0_type*) 0xf0101050u)	/* Input Class Register 0  */
#define ADC0_INPCR1	(*(ADC0_INPCR0_type*) 0xf0101054u)	/* Input Class Register 1  */
#define ADC0_INPCR2	(*(ADC0_INPCR0_type*) 0xf0101058u)	/* Input Class Register 2  */
#define ADC0_INPCR3	(*(ADC0_INPCR0_type*) 0xf010105cu)	/* Input Class Register 3  */
#define ADC1_INPCR0	(*(ADC0_INPCR0_type*) 0xf0101450u)	/* Input Class Register 0  */
#define ADC1_INPCR1	(*(ADC0_INPCR0_type*) 0xf0101454u)	/* Input Class Register 1  */
#define ADC1_INPCR2	(*(ADC0_INPCR0_type*) 0xf0101458u)	/* Input Class Register 2  */
#define ADC1_INPCR3	(*(ADC0_INPCR0_type*) 0xf010145cu)	/* Input Class Register 3  */

typedef volatile union
{
	struct
	{ 
		unsigned int SISR0          : 1;
		unsigned int SISR1          : 1;
		unsigned int SISR2          : 1;
		unsigned int SISR3          : 1;
		unsigned int SISR4          : 1;
		unsigned int SISR5          : 1;
		unsigned int SISR6          : 1;
		unsigned int SISR7          : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} ADC0_INTR_type;
#define ADC0_INTR	(*(ADC0_INTR_type*) 0xf0101204u)	/* Interrupt Activation Register  */
#define ADC1_INTR	(*(ADC0_INTR_type*) 0xf0101604u)	/* Interrupt Activation Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 2;
		/* const */ unsigned int ACK            : 1;
		/* const */ unsigned int SUSREQ         : 1;
		unsigned int NOMCFG         : 2;
		unsigned int                : 1;
		unsigned int BPNOM          : 1;
		unsigned int SUMCFG         : 2;
		unsigned int                : 1;
		unsigned int BPSUM          : 1;
		unsigned int                : 20;
	} B;
	int I;
	unsigned int U;

} ADC0_KSCFG_type;
#define ADC0_KSCFG	(*(ADC0_KSCFG_type*) 0xf010100cu)	/* Kernel State Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 2;
		unsigned int BOUNDARY       : 10;
		unsigned int                : 20;
	} B;
	int I;
	unsigned int U;

} ADC0_LCBR0_type;
#define ADC0_LCBR0	(*(ADC0_LCBR0_type*) 0xf01010f0u)	/* Limit Check Boundary Register 0  */
#define ADC0_LCBR1	(*(ADC0_LCBR0_type*) 0xf01010f4u)	/* Limit Check Boundary Register 1  */
#define ADC0_LCBR2	(*(ADC0_LCBR0_type*) 0xf01010f8u)	/* Limit Check Boundary Register 2  */
#define ADC0_LCBR3	(*(ADC0_LCBR0_type*) 0xf01010fcu)	/* Limit Check Boundary Register 3  */
#define ADC1_LCBR0	(*(ADC0_LCBR0_type*) 0xf01014f0u)	/* Limit Check Boundary Register 0  */
#define ADC1_LCBR1	(*(ADC0_LCBR0_type*) 0xf01014f4u)	/* Limit Check Boundary Register 1  */
#define ADC1_LCBR2	(*(ADC0_LCBR0_type*) 0xf01014f8u)	/* Limit Check Boundary Register 2  */
#define ADC1_LCBR3	(*(ADC0_LCBR0_type*) 0xf01014fcu)	/* Limit Check Boundary Register 3  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int REQCHNR        : 4;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int RF             : 1;
		/* const */ unsigned int ENSI           : 1;
		/* const */ unsigned int EXTR           : 1;
		/* const */ unsigned int V              : 1;
		/* const */ unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} ADC0_Q0R0_type;
#define ADC0_Q0R0	(*(ADC0_Q0R0_type*) 0xf0101088u)	/* Queue 0 Register 0  */
#define ADC0_Q0R2	(*(ADC0_Q0R0_type*) 0xf01010a8u)	/* Queue 2 Register 0  */
#define ADC0_Q0R4	(*(ADC0_Q0R0_type*) 0xf01010c8u)	/* Queue 4 Register 0  */
#define ADC0_QBUR0	(*(ADC0_Q0R0_type*) 0xf010108cu)	/* Queue 0 Backup Register  */
#define ADC0_QBUR2	(*(ADC0_Q0R0_type*) 0xf01010acu)	/* Queue 2 Backup Register  */
#define ADC0_QBUR4	(*(ADC0_Q0R0_type*) 0xf01010ccu)	/* Queue 4 Backup Register  */
#define ADC1_Q0R0	(*(ADC0_Q0R0_type*) 0xf0101488u)	/* Queue 0 Register 0  */
#define ADC1_Q0R2	(*(ADC0_Q0R0_type*) 0xf01014a8u)	/* Queue 2 Register 0  */
#define ADC1_Q0R4	(*(ADC0_Q0R0_type*) 0xf01014c8u)	/* Queue 4 Register 0  */
#define ADC1_QBUR0	(*(ADC0_Q0R0_type*) 0xf010148cu)	/* Queue 0 Backup Register  */
#define ADC1_QBUR2	(*(ADC0_Q0R0_type*) 0xf01014acu)	/* Queue 2 Backup Register  */
#define ADC1_QBUR4	(*(ADC0_Q0R0_type*) 0xf01014ccu)	/* Queue 4 Backup Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int REQCHNR        : 4;
		unsigned int                : 1;
		unsigned int RF             : 1;
		unsigned int ENSI           : 1;
		unsigned int EXTR           : 1;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} ADC0_QINR0_type;
#define ADC0_QINR0	(*(ADC0_QINR0_type*) 0xf010108cu)	/* Queue 0 Input Register  */
#define ADC0_QINR2	(*(ADC0_QINR0_type*) 0xf01010acu)	/* Queue 2 Input Register  */
#define ADC0_QINR4	(*(ADC0_QINR0_type*) 0xf01010ccu)	/* Queue 4 Input Register  */
#define ADC1_QINR0	(*(ADC0_QINR0_type*) 0xf010148cu)	/* Queue 0 Input Register  */
#define ADC1_QINR2	(*(ADC0_QINR0_type*) 0xf01014acu)	/* Queue 2 Input Register  */
#define ADC1_QINR4	(*(ADC0_QINR0_type*) 0xf01014ccu)	/* Queue 4 Input Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ENGT           : 2;
		unsigned int ENTR           : 1;
		unsigned int                : 5;
		unsigned int CLRV           : 1;
		unsigned int TREV           : 1;
		unsigned int FLUSH          : 1;
		unsigned int CEV            : 1;
		unsigned int                : 20;
	} B;
	int I;
	unsigned int U;

} ADC0_QMR0_type;
#define ADC0_QMR0	(*(ADC0_QMR0_type*) 0xf0101080u)	/* Queue 0 Mode Register  */
#define ADC0_QMR2	(*(ADC0_QMR0_type*) 0xf01010a0u)	/* Queue 2 Mode Register  */
#define ADC0_QMR4	(*(ADC0_QMR0_type*) 0xf01010c0u)	/* Queue 4 Mode Register  */
#define ADC1_QMR0	(*(ADC0_QMR0_type*) 0xf0101480u)	/* Queue 0 Mode Register  */
#define ADC1_QMR2	(*(ADC0_QMR0_type*) 0xf01014a0u)	/* Queue 2 Mode Register  */
#define ADC1_QMR4	(*(ADC0_QMR0_type*) 0xf01014c0u)	/* Queue 4 Mode Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int FILL           : 4;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int EMPTY          : 1;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int REQGT          : 1;
		/* const */ unsigned int EV             : 1;
		/* const */ unsigned int                : 23;
	} B;
	int I;
	unsigned int U;

} ADC0_QSR0_type;
#define ADC0_QSR0	(*(ADC0_QSR0_type*) 0xf0101084u)	/* Queue 0 Status Register  */
#define ADC0_QSR2	(*(ADC0_QSR0_type*) 0xf01010a4u)	/* Queue 2 Status Register  */
#define ADC0_QSR4	(*(ADC0_QSR0_type*) 0xf01010c4u)	/* Queue 4 Status Register  */
#define ADC1_QSR0	(*(ADC0_QSR0_type*) 0xf0101484u)	/* Queue 0 Status Register  */
#define ADC1_QSR2	(*(ADC0_QSR0_type*) 0xf01014a4u)	/* Queue 2 Status Register  */
#define ADC1_QSR4	(*(ADC0_QSR0_type*) 0xf01014c4u)	/* Queue 4 Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DRCTR          : 2;
		unsigned int                : 2;
		unsigned int ENRI           : 1;
		unsigned int FEN            : 1;
		unsigned int WFR            : 1;
		unsigned int                : 25;
	} B;
	int I;
	unsigned int U;

} ADC0_RCR0_type;
#define ADC0_RCR0	(*(ADC0_RCR0_type*) 0xf0101140u)	/* Result Control Register 0  */
#define ADC0_RCR1	(*(ADC0_RCR0_type*) 0xf0101144u)	/* Result Control Register 1  */
#define ADC0_RCR10	(*(ADC0_RCR0_type*) 0xf0101168u)	/* Result Control Register 10  */
#define ADC0_RCR11	(*(ADC0_RCR0_type*) 0xf010116cu)	/* Result Control Register 11  */
#define ADC0_RCR12	(*(ADC0_RCR0_type*) 0xf0101170u)	/* Result Control Register 12  */
#define ADC0_RCR13	(*(ADC0_RCR0_type*) 0xf0101174u)	/* Result Control Register 13  */
#define ADC0_RCR14	(*(ADC0_RCR0_type*) 0xf0101178u)	/* Result Control Register 14  */
#define ADC0_RCR15	(*(ADC0_RCR0_type*) 0xf010117cu)	/* Result Control Register 15  */
#define ADC0_RCR2	(*(ADC0_RCR0_type*) 0xf0101148u)	/* Result Control Register 2  */
#define ADC0_RCR3	(*(ADC0_RCR0_type*) 0xf010114cu)	/* Result Control Register 3  */
#define ADC0_RCR4	(*(ADC0_RCR0_type*) 0xf0101150u)	/* Result Control Register 4  */
#define ADC0_RCR5	(*(ADC0_RCR0_type*) 0xf0101154u)	/* Result Control Register 5  */
#define ADC0_RCR6	(*(ADC0_RCR0_type*) 0xf0101158u)	/* Result Control Register 6  */
#define ADC0_RCR7	(*(ADC0_RCR0_type*) 0xf010115cu)	/* Result Control Register 7  */
#define ADC0_RCR8	(*(ADC0_RCR0_type*) 0xf0101160u)	/* Result Control Register 8  */
#define ADC0_RCR9	(*(ADC0_RCR0_type*) 0xf0101164u)	/* Result Control Register 9  */
#define ADC1_RCR0	(*(ADC0_RCR0_type*) 0xf0101540u)	/* Result Control Register 0  */
#define ADC1_RCR1	(*(ADC0_RCR0_type*) 0xf0101544u)	/* Result Control Register 1  */
#define ADC1_RCR10	(*(ADC0_RCR0_type*) 0xf0101568u)	/* Result Control Register 10  */
#define ADC1_RCR11	(*(ADC0_RCR0_type*) 0xf010156cu)	/* Result Control Register 11  */
#define ADC1_RCR12	(*(ADC0_RCR0_type*) 0xf0101570u)	/* Result Control Register 12  */
#define ADC1_RCR13	(*(ADC0_RCR0_type*) 0xf0101574u)	/* Result Control Register 13  */
#define ADC1_RCR14	(*(ADC0_RCR0_type*) 0xf0101578u)	/* Result Control Register 14  */
#define ADC1_RCR15	(*(ADC0_RCR0_type*) 0xf010157cu)	/* Result Control Register 15  */
#define ADC1_RCR2	(*(ADC0_RCR0_type*) 0xf0101548u)	/* Result Control Register 2  */
#define ADC1_RCR3	(*(ADC0_RCR0_type*) 0xf010154cu)	/* Result Control Register 3  */
#define ADC1_RCR4	(*(ADC0_RCR0_type*) 0xf0101550u)	/* Result Control Register 4  */
#define ADC1_RCR5	(*(ADC0_RCR0_type*) 0xf0101554u)	/* Result Control Register 5  */
#define ADC1_RCR6	(*(ADC0_RCR0_type*) 0xf0101558u)	/* Result Control Register 6  */
#define ADC1_RCR7	(*(ADC0_RCR0_type*) 0xf010155cu)	/* Result Control Register 7  */
#define ADC1_RCR8	(*(ADC0_RCR0_type*) 0xf0101560u)	/* Result Control Register 8  */
#define ADC1_RCR9	(*(ADC0_RCR0_type*) 0xf0101564u)	/* Result Control Register 9  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RESULT         : 14;
		/* const */ unsigned int                : 2;
		/* const */ unsigned int EMUX           : 3;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int CRS            : 3;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int CHNR           : 4;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int DRC            : 2;
		/* const */ unsigned int VF             : 1;
	} B;
	int I;
	unsigned int U;

} ADC0_RESR0_type;
#define ADC0_RESR0	(*(ADC0_RESR0_type*) 0xf0101180u)	/* Result Register 0  */
#define ADC0_RESRD0	(*(ADC0_RESR0_type*) 0xf01011c0u)	/* Result Register 0 for Debugging  */
#define ADC1_RESR0	(*(ADC0_RESR0_type*) 0xf0101580u)	/* Result Register 0  */
#define ADC1_RESRD0	(*(ADC0_RESR0_type*) 0xf01015c0u)	/* Result Register 0 for Debugging  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int RESULT         : 14;
		/* const */ unsigned int                : 6;
		/* const */ unsigned int CRS            : 3;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int CHNR           : 4;
		/* const */ unsigned int                : 1;
		/* const */ unsigned int DRC            : 2;
		/* const */ unsigned int VF             : 1;
	} B;
	int I;
	unsigned int U;

} ADC0_RESR1_type;
#define ADC0_RESR1	(*(ADC0_RESR1_type*) 0xf0101184u)	/* Result Register 1  */
#define ADC0_RESR10	(*(ADC0_RESR1_type*) 0xf01011a8u)	/* Result Register 10  */
#define ADC0_RESR11	(*(ADC0_RESR1_type*) 0xf01011acu)	/* Result Register 11  */
#define ADC0_RESR12	(*(ADC0_RESR1_type*) 0xf01011b0u)	/* Result Register 12  */
#define ADC0_RESR13	(*(ADC0_RESR1_type*) 0xf01011b4u)	/* Result Register 13  */
#define ADC0_RESR14	(*(ADC0_RESR1_type*) 0xf01011b8u)	/* Result Register 14  */
#define ADC0_RESR15	(*(ADC0_RESR1_type*) 0xf01011bcu)	/* Result Register 15  */
#define ADC0_RESR2	(*(ADC0_RESR1_type*) 0xf0101188u)	/* Result Register 2  */
#define ADC0_RESR3	(*(ADC0_RESR1_type*) 0xf010118cu)	/* Result Register 3  */
#define ADC0_RESR4	(*(ADC0_RESR1_type*) 0xf0101190u)	/* Result Register 4  */
#define ADC0_RESR5	(*(ADC0_RESR1_type*) 0xf0101194u)	/* Result Register 5  */
#define ADC0_RESR6	(*(ADC0_RESR1_type*) 0xf0101198u)	/* Result Register 6  */
#define ADC0_RESR7	(*(ADC0_RESR1_type*) 0xf010119cu)	/* Result Register 7  */
#define ADC0_RESR8	(*(ADC0_RESR1_type*) 0xf01011a0u)	/* Result Register 8  */
#define ADC0_RESR9	(*(ADC0_RESR1_type*) 0xf01011a4u)	/* Result Register 9  */
#define ADC0_RESRD1	(*(ADC0_RESR1_type*) 0xf01011c4u)	/* Result Register 1 for Debugging  */
#define ADC0_RESRD10	(*(ADC0_RESR1_type*) 0xf01011e8u)	/* Result Register 10 for Debugging  */
#define ADC0_RESRD11	(*(ADC0_RESR1_type*) 0xf01011ecu)	/* Result Register 11 for Debugging  */
#define ADC0_RESRD12	(*(ADC0_RESR1_type*) 0xf01011f0u)	/* Result Register 12 for Debugging  */
#define ADC0_RESRD13	(*(ADC0_RESR1_type*) 0xf01011f4u)	/* Result Register 13 for Debugging  */
#define ADC0_RESRD14	(*(ADC0_RESR1_type*) 0xf01011f8u)	/* Result Register 14 for Debugging  */
#define ADC0_RESRD15	(*(ADC0_RESR1_type*) 0xf01011fcu)	/* Result Register 15 for Debugging  */
#define ADC0_RESRD2	(*(ADC0_RESR1_type*) 0xf01011c8u)	/* Result Register 2 for Debugging  */
#define ADC0_RESRD3	(*(ADC0_RESR1_type*) 0xf01011ccu)	/* Result Register 3 for Debugging  */
#define ADC0_RESRD4	(*(ADC0_RESR1_type*) 0xf01011d0u)	/* Result Register 4 for Debugging  */
#define ADC0_RESRD5	(*(ADC0_RESR1_type*) 0xf01011d4u)	/* Result Register 5 for Debugging  */
#define ADC0_RESRD6	(*(ADC0_RESR1_type*) 0xf01011d8u)	/* Result Register 6 for Debugging  */
#define ADC0_RESRD7	(*(ADC0_RESR1_type*) 0xf01011dcu)	/* Result Register 7 for Debugging  */
#define ADC0_RESRD8	(*(ADC0_RESR1_type*) 0xf01011e0u)	/* Result Register 8 for Debugging  */
#define ADC0_RESRD9	(*(ADC0_RESR1_type*) 0xf01011e4u)	/* Result Register 9 for Debugging  */
#define ADC1_RESR1	(*(ADC0_RESR1_type*) 0xf0101584u)	/* Result Register 1  */
#define ADC1_RESR10	(*(ADC0_RESR1_type*) 0xf01015a8u)	/* Result Register 10  */
#define ADC1_RESR11	(*(ADC0_RESR1_type*) 0xf01015acu)	/* Result Register 11  */
#define ADC1_RESR12	(*(ADC0_RESR1_type*) 0xf01015b0u)	/* Result Register 12  */
#define ADC1_RESR13	(*(ADC0_RESR1_type*) 0xf01015b4u)	/* Result Register 13  */
#define ADC1_RESR14	(*(ADC0_RESR1_type*) 0xf01015b8u)	/* Result Register 14  */
#define ADC1_RESR15	(*(ADC0_RESR1_type*) 0xf01015bcu)	/* Result Register 15  */
#define ADC1_RESR2	(*(ADC0_RESR1_type*) 0xf0101588u)	/* Result Register 2  */
#define ADC1_RESR3	(*(ADC0_RESR1_type*) 0xf010158cu)	/* Result Register 3  */
#define ADC1_RESR4	(*(ADC0_RESR1_type*) 0xf0101590u)	/* Result Register 4  */
#define ADC1_RESR5	(*(ADC0_RESR1_type*) 0xf0101594u)	/* Result Register 5  */
#define ADC1_RESR6	(*(ADC0_RESR1_type*) 0xf0101598u)	/* Result Register 6  */
#define ADC1_RESR7	(*(ADC0_RESR1_type*) 0xf010159cu)	/* Result Register 7  */
#define ADC1_RESR8	(*(ADC0_RESR1_type*) 0xf01015a0u)	/* Result Register 8  */
#define ADC1_RESR9	(*(ADC0_RESR1_type*) 0xf01015a4u)	/* Result Register 9  */
#define ADC1_RESRD1	(*(ADC0_RESR1_type*) 0xf01015c4u)	/* Result Register 1 for Debugging  */
#define ADC1_RESRD10	(*(ADC0_RESR1_type*) 0xf01015e8u)	/* Result Register 10 for Debugging  */
#define ADC1_RESRD11	(*(ADC0_RESR1_type*) 0xf01015ecu)	/* Result Register 11 for Debugging  */
#define ADC1_RESRD12	(*(ADC0_RESR1_type*) 0xf01015f0u)	/* Result Register 12 for Debugging  */
#define ADC1_RESRD13	(*(ADC0_RESR1_type*) 0xf01015f4u)	/* Result Register 13 for Debugging  */
#define ADC1_RESRD14	(*(ADC0_RESR1_type*) 0xf01015f8u)	/* Result Register 14 for Debugging  */
#define ADC1_RESRD15	(*(ADC0_RESR1_type*) 0xf01015fcu)	/* Result Register 15 for Debugging  */
#define ADC1_RESRD2	(*(ADC0_RESR1_type*) 0xf01015c8u)	/* Result Register 2 for Debugging  */
#define ADC1_RESRD3	(*(ADC0_RESR1_type*) 0xf01015ccu)	/* Result Register 3 for Debugging  */
#define ADC1_RESRD4	(*(ADC0_RESR1_type*) 0xf01015d0u)	/* Result Register 4 for Debugging  */
#define ADC1_RESRD5	(*(ADC0_RESR1_type*) 0xf01015d4u)	/* Result Register 5 for Debugging  */
#define ADC1_RESRD6	(*(ADC0_RESR1_type*) 0xf01015d8u)	/* Result Register 6 for Debugging  */
#define ADC1_RESRD7	(*(ADC0_RESR1_type*) 0xf01015dcu)	/* Result Register 7 for Debugging  */
#define ADC1_RESRD8	(*(ADC0_RESR1_type*) 0xf01015e0u)	/* Result Register 8 for Debugging  */
#define ADC1_RESRD9	(*(ADC0_RESR1_type*) 0xf01015e4u)	/* Result Register 9 for Debugging  */

typedef volatile union
{
	struct
	{ 
		unsigned int RENP0          : 3;
		unsigned int                : 1;
		unsigned int RENP1          : 3;
		unsigned int                : 1;
		unsigned int RENP2          : 3;
		unsigned int                : 1;
		unsigned int RENP3          : 3;
		unsigned int                : 1;
		unsigned int RENP4          : 3;
		unsigned int                : 1;
		unsigned int RENP5          : 3;
		unsigned int                : 1;
		unsigned int RENP6          : 3;
		unsigned int                : 1;
		unsigned int RENP7          : 3;
		unsigned int                : 1;
	} B;
	int I;
	unsigned int U;

} ADC0_RNPR0_type;
#define ADC0_RNPR0	(*(ADC0_RNPR0_type*) 0xf0101208u)	/* Result Node Pointer Register 0  */
#define ADC1_RNPR0	(*(ADC0_RNPR0_type*) 0xf0101608u)	/* Result Node Pointer Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int RENP8          : 3;
		unsigned int                : 1;
		unsigned int RENP9          : 3;
		unsigned int                : 1;
		unsigned int RENP10         : 3;
		unsigned int                : 1;
		unsigned int RENP11         : 3;
		unsigned int                : 1;
		unsigned int RENP12         : 3;
		unsigned int                : 1;
		unsigned int RENP13         : 3;
		unsigned int                : 1;
		unsigned int RENP14         : 3;
		unsigned int                : 1;
		unsigned int RENP15         : 3;
		unsigned int                : 1;
	} B;
	int I;
	unsigned int U;

} ADC0_RNPR8_type;
#define ADC0_RNPR8	(*(ADC0_RNPR8_type*) 0xf010120cu)	/* Result Node Pointer Register 8  */
#define ADC1_RNPR8	(*(ADC0_RNPR8_type*) 0xf010160cu)	/* Result Node Pointer Register 8  */

typedef volatile union
{
	struct
	{ 
		unsigned int GTSEL          : 3;
		unsigned int                : 1;
		unsigned int TMEN           : 1;
		unsigned int                : 2;
		/* const */ unsigned int GTI            : 1;
		unsigned int TRSEL          : 3;
		unsigned int                : 1;
		unsigned int FEN            : 1;
		unsigned int REN            : 1;
		unsigned int                : 1;
		/* const */ unsigned int TRI            : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_RSIR0_type;
#define ADC0_RSIR0	(*(ADC0_RSIR0_type*) 0xf0101010u)	/* Request Source 0 Input Register  */
#define ADC0_RSIR1	(*(ADC0_RSIR0_type*) 0xf0101014u)	/* Request Source 0 Input Register  */
#define ADC0_RSIR2	(*(ADC0_RSIR0_type*) 0xf0101018u)	/* Request Source 0 Input Register  */
#define ADC0_RSIR3	(*(ADC0_RSIR0_type*) 0xf010101cu)	/* Request Source 0 Input Register  */
#define ADC0_RSIR4	(*(ADC0_RSIR0_type*) 0xf0101020u)	/* Request Source 0 Input Register  */
#define ADC1_RSIR0	(*(ADC0_RSIR0_type*) 0xf0101410u)	/* Request Source 0 Input Register  */
#define ADC1_RSIR1	(*(ADC0_RSIR0_type*) 0xf0101414u)	/* Request Source 0 Input Register  */
#define ADC1_RSIR2	(*(ADC0_RSIR0_type*) 0xf0101418u)	/* Request Source 0 Input Register  */
#define ADC1_RSIR3	(*(ADC0_RSIR0_type*) 0xf010141cu)	/* Request Source 0 Input Register  */
#define ADC1_RSIR4	(*(ADC0_RSIR0_type*) 0xf0101420u)	/* Request Source 0 Input Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int PRIO0          : 2;
		unsigned int                : 1;
		unsigned int CSM0           : 1;
		unsigned int PRIO1          : 2;
		unsigned int                : 1;
		unsigned int CSM1           : 1;
		unsigned int PRIO2          : 2;
		unsigned int                : 1;
		unsigned int CSM2           : 1;
		unsigned int PRIO3          : 2;
		unsigned int                : 1;
		unsigned int CSM3           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_RSPR0_type;
#define ADC0_RSPR0	(*(ADC0_RSPR0_type*) 0xf0101040u)	/* Request Source Priority Register 0  */
#define ADC1_RSPR0	(*(ADC0_RSPR0_type*) 0xf0101440u)	/* Request Source Priority Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned int PRIO4          : 2;
		unsigned int                : 1;
		unsigned int CSM4           : 1;
		unsigned int                : 28;
	} B;
	int I;
	unsigned int U;

} ADC0_RSPR4_type;
#define ADC0_RSPR4	(*(ADC0_RSPR4_type*) 0xf0101044u)	/* Request Source Priority Register 4  */
#define ADC1_RSPR4	(*(ADC0_RSPR4_type*) 0xf0101444u)	/* Request Source Priority Register 4  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_SRC0_type;
#define ADC0_SRC0	(*(ADC0_SRC0_type*) 0xf01013fcu)	/* ADC Service Request Control Register 0  */
#define ADC0_SRC1	(*(ADC0_SRC0_type*) 0xf01013f8u)	/* ADC Service Request Control Register 1  */
#define ADC0_SRC2	(*(ADC0_SRC0_type*) 0xf01013f4u)	/* ADC Service Request Control Register 2  */
#define ADC0_SRC3	(*(ADC0_SRC0_type*) 0xf01013f0u)	/* ADC Service Request Control Register 3  */
#define ADC0_SRC4	(*(ADC0_SRC0_type*) 0xf01013ecu)	/* ADC Service Request Control Register 4  */
#define ADC0_SRC5	(*(ADC0_SRC0_type*) 0xf01013e8u)	/* ADC Service Request Control Register 5  */

typedef volatile union
{
	struct
	{ 
		unsigned int STSEL          : 2;
		unsigned int                : 2;
		unsigned int EVALR1         : 1;
		unsigned int EVALR2         : 1;
		unsigned int EVALR3         : 1;
		unsigned int                : 25;
	} B;
	int I;
	unsigned int U;

} ADC0_SYNCTR_type;
#define ADC0_SYNCTR	(*(ADC0_SYNCTR_type*) 0xf0101048u)	/* Synchronization Control Register  */
#define ADC1_SYNCTR	(*(ADC0_SYNCTR_type*) 0xf0101448u)	/* Synchronization Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int VF0            : 1;
		unsigned int VF1            : 1;
		unsigned int VF2            : 1;
		unsigned int VF3            : 1;
		unsigned int VF4            : 1;
		unsigned int VF5            : 1;
		unsigned int VF6            : 1;
		unsigned int VF7            : 1;
		unsigned int VF8            : 1;
		unsigned int VF9            : 1;
		unsigned int VF10           : 1;
		unsigned int VF11           : 1;
		unsigned int VF12           : 1;
		unsigned int VF13           : 1;
		unsigned int VF14           : 1;
		unsigned int VF15           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} ADC0_VFR_type;
#define ADC0_VFR	(*(ADC0_VFR_type*) 0xf0101200u)	/* Valid Flag Register  */
#define ADC1_VFR	(*(ADC0_VFR_type*) 0xf0101600u)	/* Valid Flag Register  */


/* FADC */
typedef volatile union
{
	struct
	{ 
		unsigned int GAIN           : 2;
		unsigned int ENP            : 1;
		unsigned int ENN            : 1;
		unsigned int                : 4;
		unsigned int CALOFF_2_0_    : 3;
		unsigned int                : 1;
		unsigned int CALOFF3        : 1;
		unsigned int CALGAIN        : 2;
		unsigned int                : 17;
	} B;
	int I;
	unsigned int U;

} FADC_ACR0_type;
#define FADC_ACR0	(*(FADC_ACR0_type*) 0xf0100430u)	/* Channel 0 Analog Control Register  */
#define FADC_ACR1	(*(FADC_ACR0_type*) 0xf0100434u)	/* Channel 1 Analog Control Register  */
#define FADC_ACR2	(*(FADC_ACR0_type*) 0xf0100438u)	/* Channel 2 Analog Control Register  */
#define FADC_ACR3	(*(FADC_ACR0_type*) 0xf010043cu)	/* Channel 3 Analog Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ALIAS0         : 2;
		unsigned int ALIAS1         : 2;
		unsigned int ALIAS2         : 2;
		unsigned int ALIAS3         : 2;
		unsigned int                : 24;
	} B;
	int I;
	unsigned int U;

} FADC_ALR_type;
#define FADC_ALR	(*(FADC_ALR_type*) 0xf0100454u)	/* Alias Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int GSEL           : 3;
		unsigned int TSEL           : 3;
		unsigned int GM             : 2;
		unsigned int TM             : 2;
		unsigned int CTM            : 2;
		unsigned int CTF            : 3;
		unsigned int                : 1;
		unsigned int CTREL          : 8;
		unsigned int                : 4;
		unsigned int INP            : 2;
		unsigned int                : 1;
		unsigned int IEN            : 1;
	} B;
	int I;
	unsigned int U;

} FADC_CFGR0_type;
#define FADC_CFGR0	(*(FADC_CFGR0_type*) 0xf0100420u)	/* Channel 0 Configuration Register  */
#define FADC_CFGR1	(*(FADC_CFGR0_type*) 0xf0100424u)	/* Channel 1 Configuration Register  */
#define FADC_CFGR2	(*(FADC_CFGR0_type*) 0xf0100428u)	/* Channel 2 Configuration Register  */
#define FADC_CFGR3	(*(FADC_CFGR0_type*) 0xf010042cu)	/* Channel 3 Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int DISR           : 1;
		/* const */ unsigned int DISS           : 1;
		unsigned int SPEN           : 1;
		unsigned int EDIS           : 1;
		unsigned int SBWE           : 1;
		unsigned int FSOE           : 1;
		unsigned int                : 26;
	} B;
	int I;
	unsigned int U;

} FADC_CLC_type;
#define FADC_CLC	(*(FADC_CLC_type*) 0xf0100400u)	/* Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int CR0            : 19;
		/* const */ unsigned int                : 5;

		/* const */ unsigned int                : 1;
		/* const */ unsigned int MAVS           : 2;
		/* const */ unsigned int                : 2;
	} B;
	int I;
	unsigned int U;

} FADC_CRR0_type;
#define FADC_CRR0	(*(FADC_CRR0_type*) 0xf0100464u)	/* Filter 0 Current Result Register  */
#define FADC_CRR1	(*(FADC_CRR0_type*) 0xf0100484u)	/* Filter 1 Current Result Register  */
#define FADC_CRR2	(*(FADC_CRR0_type*) 0xf01004a4u)	/* Filter 2 Current Result Register  */
#define FADC_CRR3	(*(FADC_CRR0_type*) 0xf01004c4u)	/* Filter 3 Current Result Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int CRF0           : 1;
		/* const */ unsigned int CRF1           : 1;
		/* const */ unsigned int CRF2           : 1;
		/* const */ unsigned int CRF3           : 1;
		/* const */ unsigned int                : 4;
		/* const */ unsigned int BSY0           : 1;
		/* const */ unsigned int BSY1           : 1;
		/* const */ unsigned int BSY2           : 1;
		/* const */ unsigned int BSY3           : 1;
		/* const */ unsigned int                : 4;
		/* const */ unsigned int IRQ0           : 1;
		/* const */ unsigned int IRQ1           : 1;
		/* const */ unsigned int IRQ2           : 1;
		/* const */ unsigned int IRQ3           : 1;
		/* const */ unsigned int IRQF0          : 1;
		/* const */ unsigned int IRQF1          : 1;
		/* const */ unsigned int IRQF2          : 1;
		/* const */ unsigned int IRQF3          : 1;
		/* const */ unsigned int                : 8;
	} B;
	int I;
	unsigned int U;

} FADC_CRSR_type;
#define FADC_CRSR	(*(FADC_CRSR_type*) 0xf0100410u)	/* Conversion Request Status Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ADDL           : 3;
		unsigned int                : 1;
		unsigned int MAVL           : 2;
		unsigned int                : 2;
		unsigned int INSEL          : 3;
		unsigned int                : 1;
		unsigned int INP            : 2;
		unsigned int                : 1;
		unsigned int IEN            : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} FADC_FCR0_type;
#define FADC_FCR0	(*(FADC_FCR0_type*) 0xf0100460u)	/* Filter 0 Control Register  */
#define FADC_FCR1	(*(FADC_FCR0_type*) 0xf0100480u)	/* Filter 1 Control Register  */
#define FADC_FCR2	(*(FADC_FCR0_type*) 0xf01004a0u)	/* Filter 2 Control Register  */
#define FADC_FCR3	(*(FADC_FCR0_type*) 0xf01004c0u)	/* Filter 3 Control Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int STEP           : 10;
		unsigned int                : 1;
		unsigned int SM             : 1;
		unsigned int SC             : 2;
		unsigned int DM             : 2;
		/* const */ unsigned int RESULT         : 10;
		unsigned int                : 2;
		/* const */ unsigned int SUSACK         : 1;
		/* const */ unsigned int SUSREQ         : 1;
		unsigned int ENHW           : 1;
		unsigned int DISCLK         : 1;
	} B;
	int I;
	unsigned int U;

} FADC_FDR_type;
#define FADC_FDR	(*(FADC_FDR_type*) 0xf010040cu)	/* Fractional Divider Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int RCRF0          : 1;
		unsigned int RCRF1          : 1;
		unsigned int RCRF2          : 1;
		unsigned int RCRF3          : 1;
		unsigned int                : 4;
		unsigned int SCRF0          : 1;
		unsigned int SCRF1          : 1;
		unsigned int SCRF2          : 1;
		unsigned int SCRF3          : 1;
		unsigned int                : 4;
		unsigned int RIRQ0          : 1;
		unsigned int RIRQ1          : 1;
		unsigned int RIRQ2          : 1;
		unsigned int RIRQ3          : 1;
		unsigned int RIRQF0         : 1;
		unsigned int RIRQF1         : 1;
		unsigned int RIRQF2         : 1;
		unsigned int RIRQF3         : 1;
		unsigned int SIRQ0          : 1;
		unsigned int SIRQ1          : 1;
		unsigned int SIRQ2          : 1;
		unsigned int SIRQ3          : 1;
		unsigned int SIRQF0         : 1;
		unsigned int SIRQF1         : 1;
		unsigned int SIRQF2         : 1;
		unsigned int SIRQF3         : 1;
	} B;
	int I;
	unsigned int U;

} FADC_FMR_type;
#define FADC_FMR	(*(FADC_FMR_type*) 0xf0100414u)	/* Flag Modification Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int FR             : 15;
		/* const */ unsigned int                : 17;
	} B;
	int I;
	unsigned int U;

} FADC_FRR0_type;
#define FADC_FRR0	(*(FADC_FRR0_type*) 0xf0100474u)	/* Filter 0 Final Result Register  */
#define FADC_FRR2	(*(FADC_FRR0_type*) 0xf01004b4u)	/* Filter 2 Final Result Register  */
#define FADC_SFRR1	(*(FADC_FRR0_type*) 0xf0100498u)	/* Filter 1 Shifted Final Result Register  */
#define FADC_SFRR3	(*(FADC_FRR0_type*) 0xf01004d8u)	/* Filter 3 Shifted Final Result Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int FR             : 20;
		/* const */ unsigned int                : 12;
	} B;
	int I;
	unsigned int U;

} FADC_FRR1_type;
#define FADC_FRR1	(*(FADC_FRR1_type*) 0xf0100494u)	/* Filter 1 Final Result Register  */
#define FADC_FRR3	(*(FADC_FRR1_type*) 0xf01004d4u)	/* Filter 3 Final Result Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int RCT0           : 1;
		unsigned int RCT1           : 1;
		unsigned int RCT2           : 1;
		unsigned int RCT3           : 1;
		unsigned int                : 4;
		unsigned int RCD            : 1;
		unsigned int RSTF0          : 1;
		unsigned int RSTF1          : 1;
		unsigned int RSTF2          : 1;
		unsigned int RSTF3          : 1;
		unsigned int                : 3;
		unsigned int CRPRIO         : 2;
		unsigned int DPAEN          : 1;
		unsigned int RESWEN         : 1;
		unsigned int MUXTM          : 1;
		unsigned int ANON           : 1;
		unsigned int                : 2;
		unsigned int CALMODE        : 2;
		unsigned int CALCH          : 2;
		unsigned int                : 4;
	} B;
	int I;
	unsigned int U;

} FADC_GCR_type;
#define FADC_GCR	(*(FADC_GCR_type*) 0xf010041cu)	/* Global Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int IR             : 13;
		/* const */ unsigned int                : 19;
	} B;
	int I;
	unsigned int U;

} FADC_IRR10_type;
#define FADC_IRR10	(*(FADC_IRR10_type*) 0xf0100468u)	/* Filter 0 Intermediate Result Register 1  */
#define FADC_IRR12	(*(FADC_IRR10_type*) 0xf01004a8u)	/* Filter 2 Intermediate Result Register 1  */
#define FADC_IRR20	(*(FADC_IRR10_type*) 0xf010046cu)	/* Filter 0 Intermediate Result Register 2  */
#define FADC_IRR22	(*(FADC_IRR10_type*) 0xf01004acu)	/* Filter 2 Intermediate Result Register 2  */
#define FADC_IRR30	(*(FADC_IRR10_type*) 0xf0100470u)	/* Filter 0 Intermediate Result Register 3  */
#define FADC_IRR32	(*(FADC_IRR10_type*) 0xf01004b0u)	/* Filter 2 Intermediate Result Register 3  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned int IR             : 18;
		/* const */ unsigned int                : 14;
	} B;
	int I;
	unsigned int U;

} FADC_IRR11_type;
#define FADC_IRR11	(*(FADC_IRR11_type*) 0xf0100488u)	/* Filter 1 Intermediate Result Register 1  */
#define FADC_IRR13	(*(FADC_IRR11_type*) 0xf01004c8u)	/* Filter 3 Intermediate Result Register 1  */

typedef volatile union
{
	struct
	{ 
		unsigned int                : 1;
		unsigned int EN01           : 1;
		unsigned int EN02           : 1;
		unsigned int EN03           : 1;
		unsigned int                : 4;
		unsigned int EN10           : 1;
		unsigned int                : 1;
		unsigned int EN12           : 1;
		unsigned int EN13           : 1;
		unsigned int                : 4;
		unsigned int EN20           : 1;
		unsigned int EN21           : 1;
		unsigned int                : 1;
		unsigned int EN23           : 1;
		unsigned int                : 4;
		unsigned int EN30           : 1;
		unsigned int EN31           : 1;
		unsigned int EN32           : 1;
		unsigned int                : 5;
	} B;
	int I;
	unsigned int U;

} FADC_NCTR_type;
#define FADC_NCTR	(*(FADC_NCTR_type*) 0xf0100418u)	/* Neighbor Channel Trigger Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int ADRES          : 10;
		unsigned int                : 22;
	} B;
	int I;
	unsigned int U;

} FADC_RCH0_type;
#define FADC_RCH0	(*(FADC_RCH0_type*) 0xf0100440u)	/* Channel 0 Conversion Result Register  */
#define FADC_RCH1	(*(FADC_RCH0_type*) 0xf0100444u)	/* Channel 1 Conversion Result Register  */
#define FADC_RCH2	(*(FADC_RCH0_type*) 0xf0100448u)	/* Channel 2 Conversion Result Register  */
#define FADC_RCH3	(*(FADC_RCH0_type*) 0xf010044cu)	/* Channel 3 Conversion Result Register  */

typedef volatile union
{
	struct
	{ 
		unsigned int SRPN           : 8;
		unsigned int                : 2;
		unsigned int TOS            : 1;
		unsigned int                : 1;
		unsigned int SRE            : 1;
		/* const */ unsigned int SRR            : 1;
		unsigned int CLRR           : 1;
		unsigned int SETR           : 1;
		unsigned int                : 16;
	} B;
	int I;
	unsigned int U;

} FADC_SRC0_type;
#define FADC_SRC0	(*(FADC_SRC0_type*) 0xf01004fcu)	/* Service Request Control Register 0  */
#define FADC_SRC1	(*(FADC_SRC0_type*) 0xf01004f8u)	/* Service Request Control Register 1  */
#define FADC_SRC2	(*(FADC_SRC0_type*) 0xf01004f4u)	/* Service Request Control Register 2  */
#define FADC_SRC3	(*(FADC_SRC0_type*) 0xf01004f0u)	/* Service Request Control Register 3  */


/* EBU */
typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 REGENAB        : 1;	/* Memory Region Enable */
		unsigned __sfrbit32 ALTENAB        : 1;	/* Alternate Segment Comparison Enable */
		unsigned __sfrbit32 WPROT          : 1;	/* Memory Region Write Protect */
		/* const */ unsigned __sfrbit32 RES            : 1;	/* Reserved */
		unsigned __sfrbit32 MASK           : 4;	/* Address Mask */
		unsigned __sfrbit32 ALTSEG         : 4;	/* Alternate Segment */
		unsigned __sfrbit32 BASE           : 20;	/* Base Address */
	} B;
	int I;
	unsigned int U;

} EBU_ADDRSEL0_type;
#define EBU_ADDRSEL0	(*(EBU_ADDRSEL0_type*) 0xf8000018u)	/* EBU Address Select Register 0  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 REGENAB        : 1;	/* Memory Region Enable */
		unsigned __sfrbit32 ALTENAB        : 1;	/* Alternate Segment Comparison Enable */
		unsigned __sfrbit32 WPROT          : 1;	/* Memory Region Write Protect */
		/* const */ unsigned __sfrbit32 RES            : 1;	/* Reserved */
		unsigned __sfrbit32 MASK           : 4;	/* Address Mask */
		unsigned __sfrbit32 ALTSEG         : 4;	/* Alternate Segment */
		unsigned __sfrbit32 BASE           : 20;	/* Base Address */
	} B;
	int I;
	unsigned int U;

} EBU_ADDRSEL1_type;
#define EBU_ADDRSEL1	(*(EBU_ADDRSEL1_type*) 0xf800001cu)	/* EBU Address Select Register 1  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 REGENAB        : 1;	/* Memory Region Enable */
		unsigned __sfrbit32 ALTENAB        : 1;	/* Alternate Segment Comparison Enable */
		unsigned __sfrbit32 WPROT          : 1;	/* Memory Region Write Protect */
		/* const */ unsigned __sfrbit32 RES            : 1;	/* Reserved */
		unsigned __sfrbit32 MASK           : 4;	/* Address Mask */
		unsigned __sfrbit32 ALTSEG         : 4;	/* Alternate Segment */
		unsigned __sfrbit32 BASE           : 20;	/* Base Address */
	} B;
	int I;
	unsigned int U;

} EBU_ADDRSEL2_type;
#define EBU_ADDRSEL2	(*(EBU_ADDRSEL2_type*) 0xf8000020u)	/* EBU Address Select Register 2  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 REGENAB        : 1;	/* Memory Region Enable */
		unsigned __sfrbit32 ALTENAB        : 1;	/* Alternate Segment Comparison Enable */
		unsigned __sfrbit32 WPROT          : 1;	/* Memory Region Write Protect */
		/* const */ unsigned __sfrbit32 RES            : 1;	/* Reserved */
		unsigned __sfrbit32 MASK           : 4;	/* Address Mask */
		unsigned __sfrbit32 ALTSEG         : 4;	/* Alternate Segment */
		unsigned __sfrbit32 BASE           : 20;	/* Base Address */
	} B;
	int I;
	unsigned int U;

} EBU_ADDRSEL3_type;
#define EBU_ADDRSEL3	(*(EBU_ADDRSEL3_type*) 0xf8000024u)	/* EBU Address Select Register 3  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 RDDTACS        : 4;
		unsigned __sfrbit32 RDRECOVC       : 3;
		unsigned __sfrbit32 WAITRDC        : 5;
		unsigned __sfrbit32 DATAC          : 4;
		unsigned __sfrbit32 EXTCLOCK       : 2;
		unsigned __sfrbit32 EXTDATA        : 2;
		unsigned __sfrbit32 CMDDELAY       : 4;
		unsigned __sfrbit32 AHOLDC         : 4;
		unsigned __sfrbit32 ADDRC          : 4;
	} B;
	int I;
	unsigned int U;

} EBU_BUSRAP0_type;
#define EBU_BUSRAP0	(*(EBU_BUSRAP0_type*) 0xf800002cu)	/* EBU Bus Read Access Parameter Register  */
#define EBU_BUSRAP1	(*(EBU_BUSRAP0_type*) 0xf800003cu)	/* EBU Bus Read Access Parameter Register  */
#define EBU_BUSRAP2	(*(EBU_BUSRAP0_type*) 0xf800004cu)	/* EBU Bus Read Access Parameter Register  */
#define EBU_BUSRAP3	(*(EBU_BUSRAP0_type*) 0xf800005cu)	/* EBU Bus Read Access Parameter Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 FETBLEN        : 3;
		unsigned __sfrbit32 FBBMSEL        : 1;
		unsigned __sfrbit32 BFSSS          : 1;
		unsigned __sfrbit32 FDBKEN         : 1;
		unsigned __sfrbit32 BFCMSEL        : 1;
		unsigned __sfrbit32 NAA            : 1;
		/* const */ unsigned __sfrbit32 RES1           : 8;
		unsigned __sfrbit32 ECSE           : 1;
		unsigned __sfrbit32 EBSE           : 1;
		unsigned __sfrbit32 DBA            : 1;
		unsigned __sfrbit32 WAITINV        : 1;
		unsigned __sfrbit32 BCGEN          : 2;
		unsigned __sfrbit32 PORTW          : 2;
		unsigned __sfrbit32 WAIT           : 2;
		unsigned __sfrbit32 AAP            : 1;
		/* const */ unsigned __sfrbit32 RES2           : 1;
		unsigned __sfrbit32 AGEN           : 4;
	} B;
	int I;
	unsigned int U;

} EBU_BUSRCON0_type;
#define EBU_BUSRCON0	(*(EBU_BUSRCON0_type*) 0xf8000028u)	/* EBU Bus Configuration Register  */
#define EBU_BUSRCON1	(*(EBU_BUSRCON0_type*) 0xf8000038u)	/* EBU Bus Configuration Register  */
#define EBU_BUSRCON2	(*(EBU_BUSRCON0_type*) 0xf8000048u)	/* EBU Bus Configuration Register  */
#define EBU_BUSRCON3	(*(EBU_BUSRCON0_type*) 0xf8000058u)	/* EBU Bus Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 WRDTACS        : 4;
		unsigned __sfrbit32 WRRECOVC       : 3;
		unsigned __sfrbit32 WAITWRC        : 5;
		unsigned __sfrbit32 DATAC          : 4;
		unsigned __sfrbit32 EXTCLOCK       : 2;
		unsigned __sfrbit32 EXTDATA        : 2;
		unsigned __sfrbit32 CMDDELAY       : 4;
		unsigned __sfrbit32 AHOLDC         : 4;
		unsigned __sfrbit32 ADDRC          : 4;
	} B;
	int I;
	unsigned int U;

} EBU_BUSWAP0_type;
#define EBU_BUSWAP0	(*(EBU_BUSWAP0_type*) 0xf8000034u)	/* EBU Bus Write Access Parameter Register  */
#define EBU_BUSWAP1	(*(EBU_BUSWAP0_type*) 0xf8000044u)	/* EBU Bus Write Access Parameter Register  */
#define EBU_BUSWAP2	(*(EBU_BUSWAP0_type*) 0xf8000054u)	/* EBU Bus Write Access Parameter Register  */
#define EBU_BUSWAP3	(*(EBU_BUSWAP0_type*) 0xf8000064u)	/* EBU Bus Write Access Parameter Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 FETBLEN        : 3;
		unsigned __sfrbit32 FBBMSEL        : 1;
		/* const */ unsigned __sfrbit32 RES1           : 3;
		/* const */ unsigned __sfrbit32 NAA            : 1;
		/* const */ unsigned __sfrbit32 RES2           : 8;
		unsigned __sfrbit32 ECSE           : 1;
		unsigned __sfrbit32 EBSE           : 1;
		/* const */ unsigned __sfrbit32 RES3           : 1;
		unsigned __sfrbit32 WAITINV        : 1;
		unsigned __sfrbit32 BCGEN          : 2;
		/* const */ unsigned __sfrbit32 PORTW          : 2;
		unsigned __sfrbit32 WAIT           : 2;
		unsigned __sfrbit32 AAP            : 1;
		unsigned __sfrbit32 LOCKCS         : 1;
		unsigned __sfrbit32 AGEN           : 4;
	} B;
	int I;
	unsigned int U;

} EBU_BUSWCON0_type;
#define EBU_BUSWCON0	(*(EBU_BUSWCON0_type*) 0xf8000030u)	/* EBU Bus Write Configuration Register  */
#define EBU_BUSWCON1	(*(EBU_BUSWCON0_type*) 0xf8000040u)	/* EBU Bus Write Configuration Register  */
#define EBU_BUSWCON2	(*(EBU_BUSWCON0_type*) 0xf8000050u)	/* EBU Bus Write Configuration Register  */
#define EBU_BUSWCON3	(*(EBU_BUSWCON0_type*) 0xf8000060u)	/* EBU Bus Write Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 DISR           : 1;	/* EBU Disable Request Bit */
		/* const */ unsigned __sfrbit32 DISS           : 1;	/* EBU Disable Status Bit */
		unsigned __sfrbit32                : 6;
		unsigned __sfrbit32 EPE            : 1;	/* Endinit Protection Enable */
		unsigned __sfrbit32                : 7;
		unsigned __sfrbit32 SYNC           : 1;	/* EBU Clocking Mode */
		unsigned __sfrbit32 DDR            : 1;	/* DDR Clocking Mode */
		unsigned __sfrbit32 EBUDIV         : 2;	/* EBU Clock Divide Ratio */
		/* const */ unsigned __sfrbit32 SYNCACK        : 1;	/* EBU Clocking Mode Status */
		/* const */ unsigned __sfrbit32 DDRACK         : 1;	/* DDR Clocking Mode Status */
		/* const */ unsigned __sfrbit32 EBUDIVACK      : 2;	/* EBU Clock Divide Ratio Status */
		unsigned __sfrbit32                : 8;
	} B;
	int I;
	unsigned int U;

} EBU_CLC_type;
#define EBU_CLC	(*(EBU_CLC_type*) 0xf8000000u)	/* EBU Clock Control Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 CFGEND         : 1;
		/* const */ unsigned __sfrbit32 CFGERR         : 1;
		/* const */ unsigned __sfrbit32 RES            : 29;
		unsigned __sfrbit32 EBUCFG         : 1;
	} B;
	int I;
	unsigned int U;

} EBU_EXTBOOT_type;
#define EBU_EXTBOOT	(*(EBU_EXTBOOT_type*) 0xf8000010u)	/* EBU External Boot Configuration Register  */

typedef volatile union
{
	struct
	{ 
		/* const */ unsigned __sfrbit32 STS            : 1;
		unsigned __sfrbit32 LCKABRT        : 1;
		/* const */ unsigned __sfrbit32 RES1           : 2;
		unsigned __sfrbit32 EXTLOCK        : 1;
		unsigned __sfrbit32 ARBSYNC        : 1;
		unsigned __sfrbit32 ARBMODE        : 2;
		unsigned __sfrbit32 TIMEOUTC       : 8;
		unsigned __sfrbit32 LOCKTIMEOUT    : 8;
		/* const */ unsigned __sfrbit32 RES2           : 7;
		unsigned __sfrbit32 ALE            : 1;
	} B;
	int I;
	unsigned int U;

} EBU_MODCON_type;
#define EBU_MODCON	(*(EBU_MODCON_type*) 0xf8000004u)	/* EBU Configuration Register  */

typedef volatile union
{
	struct
	{ 
		unsigned __sfrbit32 DIP            : 1;
		/* const */ unsigned __sfrbit32 RES            : 31;
	} B;
	int I;
	unsigned int U;

} EBU_USERCON_type;
#define EBU_USERCON	(*(EBU_USERCON_type*) 0xf800000cu)	/* EBU Test/Control Configuration Register  */

#define EBU_BOOTCFG	EBU_EXTBOOT
#endif /*_REGTC1782_H*/
